Special Sessions

Chip technology underpins progress across sectors such as automotive, telecommunications, finance, and healthcare. However, continued improvements in performance, efficiency, and functionality are increasingly constrained by the limits of traditional CMOS scaling and TSV-based 3D integration, challenged by scaling, memory, power, sustainability, and cost. Increasing integration density has long been a key enabler of progress in logic design. However, conventional two-dimensional CMOS scaling faces fundamental physical and economic challenges. Expanding integration into the third dimension offers a natural path forward. 3D Nanofabric introduces a disruptive alternative by enabling the simultaneous processing of N identical stacked layers, independent of the number of layers. This unique capability dramatically reduces fabrication cost and hardware footprint while unlocking new possibilities for dense, energy-efficient, and high-performance systems. This new fabrication paradigm has profound implications across the entire semiconductor design stack—from process design kits (PDKs) and physical design methodologies to logic and system architecture. Traditional EDA tools must evolve to address these cross-layer co-design challenges and opportunities. This session will bring together experts across the full design stack, spanning technology, design automation, and system architecture, to discuss the methodologies and innovations required to realize the full potential of 3D Nanofabric and shape the next era of semiconductor design. As this session covers the technology and the entire design stack, from EDA, circuit design, memory, and system architecture, it should be relevant to a large audience at ICCAD from both academia and industry.

The rapid emergence of large language models (LLMs) has transformed modern information processing, enabling unprecedented capabilities in reasoning, content generation, and human–machine interaction. However, their deployment is fundamentally constrained by the “memory wall” — the excessive cost of data movement between memory and compute units in conventional von Neumann architectures. As LLMs continue to scale in both model size and context length, this bottleneck increasingly dominates system performance, energy consumption, and scalability. Computing-in-memory (CIM) has long been viewed as a promising paradigm to address this challenge by performing computation directly within memory arrays, thereby minimizing data movement. Yet, despite its potential, CIM has traditionally been considered ill-suited for LLMs due to the inherent mismatch between the massive parameter size of LLMs and the limited capacity, precision, and reliability of emerging memory devices. This has led to a prevailing belief that CIM cannot effectively support modern generative AI workloads. This special session challenges this conventional wisdom and presents a new cross-layer perspective on how CIM can not only support but fundamentally reshape LLM system design. The key insight unifying this session is that CIM should not be viewed as a monolithic replacement for digital accelerators, but rather as a specialized substrate for selectively accelerating memory-intensive components of LLM workloads. By rethinking the mapping of LLM execution — offloading retrieval, context storage, and stochastic transformations into CIM fabrics — recent advances demonstrate that the perceived limitations of CIM can be transformed into unique advantages. The session begins with a broad architectural perspective on machine learning in memory, establishing the foundation for memory-centric computing paradigms. It then presents concrete system realizations showing how memristor-based CIM can efficiently support retrieval-augmented generation and long-context modeling in LLMs. Finally, the session highlights a deeper algorithm–hardware co-design insight: intrinsic device-level randomness, traditionally viewed as a drawback, can be directly exploited to implement advanced LLM compression techniques such as the recent breakthrough TurboQuant. Together, these talks provide a coherent and forward-looking vision in which CIM evolves from a niche accelerator into a key enabler for scalable, energy-efficient, and deployable generative AI systems. By bridging the gap between device-level characteristics and system-level design, this session aims to inspire new directions in EDA, architecture, and AI hardware research.

Chiplet-based architectures are rapidly transforming heterogeneous computing platforms for GenAI and LLMs, enabling modular scalability, technology heterogeneity, and high-performance integration. However, this shift introduces fundamental challenges across three critical dimensions: design, reliability, and security. Design challenges arise from the need for seamless interoperability, standardized interfaces, scalable design space exploration, and cross-layer hardware–software co-design across heterogeneous chiplet platforms. Reliability concerns encompass thermal management, power delivery, and advanced packaging techniques such as 2.5D/3D integration, all of which directly impact performance, yield, and long-term system robustness. At the same time, security becomes increasingly complex in disaggregated, multi-vendor environments, requiring new approaches to ensure trust, protect data movement, and mitigate emerging attack surfaces across chiplet boundaries. This special session brings together recent advances addressing these interconnected challenges, highlighting innovations in cross-layer design methodologies, reliability-aware system optimization, and secure architectures for heterogeneous AI systems. By unifying perspectives from academia and industry, the session aims to define a forward-looking roadmap for building scalable, reliable, and secure chiplet-based platforms tailored to the demands of GenAI and LLM workloads, spanning cloud, edge, and emerging embodied AI systems, and addressing timely challenges and opportunities central to the International Conference on Computer-Aided Design community.

The explosive growth of large language models (LLMs) is reshaping modern computing, driving unprecedented demands on performance, energy efficiency, scalability, and reliability. At the same time, the emergence of 2.5D and 3D heterogeneous, chiplet-based multi-die architectures is redefining the hardware substrate for next-generation systems. While these architectures offer a compelling path forward, they also introduce significant challenges, including cross-die communication bottlenecks, thermal coupling, process variability, and increased susceptibility to reliability and security threats. This special session focuses on the design of multi-chip systems that can efficiently and robustly support LLM workloads. It explores cross-layer EDA and co-design strategies for heterogeneous architectures that integrate compute, memory, and interconnect fabrics to meet the unique computational and data-movement characteristics of LLMs. By bringing together experts in EDA, testing, and hardware security, the session highlights emerging methodologies that span device, architecture, and system levels. It will examine how architectural heterogeneity and advanced integration technologies can be harnessed to deliver scalable performance, while addressing critical concerns such as testability, fault tolerance, and security in complex multi-die systems. Through this perspective, the session aims to advance a holistic vision for reliable, secure, and high-performance multi-chip computing platforms tailored for the demands of AI workloads.

As quantum computing transitions from the NISQ era to the early fault-tolerant (Early FTQC) regime, the field faces an urgent need for cross-layer design automation (QDA) methodologies that bridge algorithms, compilers, and hardware. In this emerging phase, where logical qubits will remain scarce, noisy, and resource-intensive, progress depends critically on automating key design tasks that have long been central to classical EDA: resource estimation, physical modeling, placement and routing, timing analysis, and calibration optimization. This special session brings together researchers spanning quantum architecture, compiler optimization, circuit synthesis, and device modeling to discuss how design-automation principles can accelerate the realization of Early FTQC. The session will conclude with an outlook on open-source infrastructures and benchmarking methodologies to foster reproducibility and community collaboration. Attendees will gain a holistic understanding of how design-automation concepts can drive the next leap from prototype-scale NISQ devices toward robust, scalable Early FTQC systems.

Three-dimensional integration and advanced packaging, including monolithic 3D ICs, 2.5D chiplet-based integration, and emerging 5.5D integration with glass interposers, have demonstrated strong potential to sustain system scaling beyond the limits of monolithic design. However, in contrast to the well-established RTL-to-GDS implementation flows for conventional 2D IC design, the lack of standardized implementation flows across these integration paradigms remains a fundamental bottleneck. The absence of unified implementation flows raises a high barrier to both the development and evaluation of new methodologies for 3D IC design. Researchers often rely on ad hoc assumptions, incomplete toolchains, or simplified design enablements, making it difficult to develop solutions that generalize across different integration paradigms and implementation scenarios. Moreover, inconsistent evaluation settings hinder the interpretation of results across different works, limiting the ability to understand design trade-offs and to accumulate progress toward a coherent methodology. This special session presents four complementary efforts that collectively address this challenge by advancing implementation methodologies across diverse 3D integration paradigms: open-source implementation platforms for advanced packaging and 3D ICs; a commercial-grade full-chip methodology for face-to-face 3D ICs; AI-driven multi-physics co-optimization for glass-interposer-based 5.5D systems; and multi-domain design optimization of thermally limited 3D ICs for AI and HPC systems. Together, these works highlight a clear shift from paradigm-specific solutions toward flow-level and cross-domain co-optimization, motivating the development of unified, scalable, and interpretable implementation frameworks for next-generation 3D ICs and advanced packaging. By bringing together representative efforts under shared contexts, the session provides a coherent perspective on the evolving 3D IC design space, helps clarify key challenges and research directions, and facilitates more consistent interpretation of results across integration paradigms.

Existing EDA environments have been predominantly organized around human interpretation, intervention, and control. Consequently, large language model (LLM)-based methods have thus far shown their greatest practical utility as copilots layered atop established tools and design flows. As chip design becomes increasingly heterogeneous, tool-intensive, and optimization-driven, however, there is growing interest in AI systems that can coordinate tasks across abstraction levels and operate in a closed loop with simulation, verification, and optimization. This shift is not merely a matter of incremental automation; rather, it raises a more fundamental question of how design intent, tool state, and optimization objectives should be represented, propagated, and acted upon across the EDA stack. Agentic AI is emerging as a consequential direction for EDA, pointing toward systems that can plan, orchestrate tools, and iteratively refine solutions across complex design workflows. This special session brings together experts from academia and industry to examine the opportunities and challenges of Agentic EDA across the design stack. Topics of interest include agent architectures, tool integration, human-agent collaboration, and related system and workflow considerations. More broadly, the session aims to interrogate how EDA systems and workflows may need to evolve to support increasingly capable AI agents, and what new forms of representation, interface, feedback, and evaluation may be required across the design flow. Agentic EDA is not only a new application of AI to existing tools, but also a lens through which to reconsider the foundations of future design automation, pointing toward next-generation AI-native systems for EDA.

AI-driven methodologies are rapidly transforming the design of next-generation integrated circuits, enabling new levels of automation, adaptability, and intelligence across the chip design lifecycle. As this paradigm accelerates, it exposes complex challenges in chip design spanning design, optimization, security, and reliability that AI-driven methodologies aim to address. Addressing these challenges is essential to unlock the full potential of scalable and robust design flows for emerging domains such as AI acceleration, large-scale inference, and high-performance computing. In this proposed special session, we bring together leading experts to explore cutting-edge advances in self-evolving optimization agents, automated physical design frameworks, AI-guided hardware security testing, and cross-stage reasoning for silicon quality improvement. The session aims to synthesize insights from both academia and industry, highlight opportunities for end-to-end AI integration across the design stack, and chart a forward-looking roadmap for building intelligent, reliable, and high-performance chip design systems at scale.

Generative AI is emerging as a major force in electronic design automation, with the potential to reshape not only how hardware is designed and verified, but also how these skills are taught and transferred to future generations of engineers. In digital design, large language models and related techniques are being explored for tasks such as requirements interpretation, RTL generation, code completion, testbench creation, debugging support, documentation, and design-space exploration. Although many of these capabilities are still evolving, their direction is already clear: generative AI is becoming an increasingly relevant layer in modern design workflows that can augment productivity, accelerate iteration, and make advanced design activities more accessible to less experienced users. At the same time, the growth of open-source EDA ecosystems is creating a strong foundation for experimentation, accessibility, and reproducibility. Open-source toolchains, libraries, educational infrastructures, and cloud-accessible environments enable a broader community to engage with realistic chip-design workflows without the barriers traditionally associated with commercial tools. This convergence offers a practical path toward democratizing advanced design capabilities: AI can lower the cognitive barrier to entry, while open infrastructures can reduce the operational barrier. This special session focuses on that convergence. Its central premise is that generative AI and open-source EDA should be considered together rather than as separate trends. Generative AI becomes more impactful when embedded in runnable, transparent, and reusable workflows; open-source EDA becomes more powerful when paired with intelligent assistants that help users navigate complexity, generate artifacts, explain tool outputs, and connect design intent to implementation and verification. The combination affects how quickly designers can prototype ideas, how effectively students can learn advanced concepts, how instructors can assemble modern curricula, and how institutions can expand training and talent development in semiconductor design. The session will examine concrete value across the digital design stack while emphasizing that correctness, semantic faithfulness, synthesizability, verification coverage, robustness, traceability, and explainability remain essential. Overall, it aims to provide a forward-looking and balanced perspective on how the EDA community can shape this transformation responsibly and productively.

AI-era systems increasingly rely on chiplets, advanced packaging, and 3D stacking, where power delivery, transient droop, and reliability must be managed across die boundaries and design hierarchies. A key bottleneck in scaling power integrity for such systems is the lack of a consistent abstraction and data exchange model that connects early power modeling to signoff-level IR-drop and reliability analysis. While standardized multi-level power modeling abstractions (e.g., IEEE 2416) enable architectural exploration, signoff IR-drop and electromigration data remain locked in tool-specific representations (e.g., XPGV, ROM), making correlation, reuse, and hierarchical integration difficult. This disconnect increasingly leads to late-stage correlation gaps, conservative guard-bands, and limited reuse across design hierarchies. This session presents a unified technical pipeline spanning abstraction-level modeling, hierarchical power-grid analysis (PGA), and multi-die power delivery. It begins by examining how power-model fidelity evolves across abstraction levels and how mismatches propagate into IR-drop sensitivity, timing margins, and reliability outcomes. It then introduces scalable hierarchical PGA methods that preserve signoff fidelity from IP to SoC. Extending into 3D-IC systems, the session addresses vertical PDN challenges including TSV/microbump interfaces, inter-die coupling, and thermally amplified droop. The session is structured to explicitly connect early modeling choices to downstream physical effects. Each talk presents concrete methodologies, measurable correlation insights, and practical guidance for integrating modeling, analysis, and validation across the design stack. Together, the session highlights where fidelity is lost across abstraction levels and how it can be recovered through improved modeling, aggregation, and validation. Unlike prior efforts that treat modeling, IR-drop, and packaging independently, this session focuses on their coupling across abstraction levels, hierarchy, and multi-die integration. A cross-vendor panel will debate whether the field should converge toward a hierarchical IR-drop data exchange layer or continue with tool-specific ecosystems augmented by adapters, considering fidelity, scalability, and IP protection. The timing is driven by industry shifts toward chiplets, 3D-IC integration, and early-stage power-driven design. Without a consistent methodology, teams face late-stage surprises, over-conservative guard-bands, and limited reuse across hierarchies. This session addresses that gap with both practical methods and a forward-looking path toward interoperable design flows.