Thursday, November 12, 2026

  • 2026 QCAS Quantum Computing Applications and Systems Workshop

    The QCAS 2026 Workshop addresses the systems engineering challenges of building scalable, fault-tolerant quantum computers. The field has reached an inflection point: multiple hardware platforms, including superconducting, neutral atom, and trapped-ion systems, have demonstrated below-threshold quantum error correction performance with real-time decoding. Industry roadmaps now project modular multi-chip quantum processors within the next few years, and national programs such as DARPA HARQ are investing in heterogeneous architectures that combine distinct qubit types for processing, memory, and communication. These developments collectively shift the central question from whether fault-tolerant quantum computing is possible to how systems can be engineered to achieve it at useful scale. QCAS 2026 is organized around four tracks spanning the full system stack: quantum error correction at scale, fault-tolerant compilation and resource estimation, distributed and modular architectures, and quantum control and hardware-software co-design. A distinguishing emphasis of this edition is the elevation of resource estimation as a unifying design methodology, serving as the quantum analog of design space exploration in classical EDA.

    • Yufei Ding University of California San Diego
    • Zichang He JPMorganChase
    • Tilas Kabengele The Cincinnati Insurance Companies
    • Gilles Lamant Cadence Design Systems
    • Zhiding Liang Chinese University of Hong Kong
    • Pengyu Liu Carnegie Mellon University
    • Yidong Zhou Rutgers University

  • Memory-Centric Computing for LLM Inference

    The rapid growth of large language models (LLMs) is reshaping modern AI systems, driving unprecedented demands on memory capacity, bandwidth, energy efficiency, and scalability, particularly for resource-constrained edge AI deployments. As inference workloads become increasingly memory-bound, conventional GPU-centric platforms struggle to efficiently support long-context reasoning, high-throughput serving, and large-scale deployment. Emerging paradigms such as processing-in-memory (PIM), 3D-integrated computing, heterogeneous architectures, wafer-scale systems, and hardware-software co-design offer promising alternatives for overcoming these bottlenecks.

    This workshop brings together researchers and practitioners from computer architecture, EDA, systems, compilers, machine learning, memory technologies, and industry to discuss the future of efficient AI inference. The workshop will highlight recent advances in memory-centric computing, including DRAM-based PIM, 3D-stacked PIM, and emerging non-volatile memory (NVM)-based computing architectures. Additional topics include heterogeneous CPU/GPU/NPU-PIM systems, wafer-scale AI computing, memory hierarchy optimization, compiler and runtime support, algorithm-system co-design, and EDA tools for scalable and energy-efficient LLM inference.

    • Chenchen Liu Beihang University
    • Xiaoxuan Yang University of Virginia

  • SSH-SoC: Safety and Security in Heterogeneous Open System-on-Chip Platforms

    The slowdown of technology scaling has shifted computer architecture toward heterogeneous, domain-specific systems. Modern SoCs increasingly combine custom accelerators with specialized interconnects, peripherals, and sensing components to meet demanding performance, efficiency, and real-time requirements. Open hardware and software ecosystems are accelerating this transition by enabling transparent design reuse, rapid prototyping, and reproducible validation.

    A common strategy to manage SoC complexity is hierarchical development: critical blocks are built in-house at RTL, others are generated with HLS, and highly specialized IP is integrated from third parties. While effective for productivity, this approach makes system integration the key bottleneck. Integration errors, weak specifications, and limited system-level verification can introduce serious security, safety, and performance risks, especially in mission-critical deployments.

    This workshop focuses on methods, tools, and early-stage ideas that improve trustworthy integration of next-generation heterogeneous SoCs using open platforms. We explicitly welcome AI-enabled approaches, including LLM-assisted design-space exploration, specification mining, IP integration support, verification/test generation, and security analysis. The goal is to advance open, safe, and high-performance SoC development through collaborative research and practical experimentation.

    • Luca Benini ETH-Zurich/University of Bologna
    • Brandon Reagen NYU
    • Francesco Restuccia UC San-Diego
    • Davide Rossi University of Bologna
    • Biruk Seyoum Columbia University

  • SUSHI’26: Sustainable Hardware Security

    The pursuit of digital sovereignty, global semiconductor shortages, and geopolitical interests drive worldwide initiatives to bolster semiconductor technology and manufacturing. Hardware security is vital at the core of all computing systems, as insecure hardware puts critical systems and society at risk.

    However, in recent years we are observing the discovery of a growing number of hardware design and implementation vulnerabilities that unprivileged software could exploit, leading to the potential exposure of sensitive data or compromise of the whole computing system. This new attack paradigm greatly shadows decades of system security research. Existing solutions are often ad-hoc, limited, inefficient, and specific.

    Tackling these challenges calls for radically new approaches to the security-by-design for hardware, security-aware electronic design automation, resilient microarchitecture and architectures, and scalable assurance.

    • Jason Fung Intel
    • Gang Qu University of Maryland
    • JV Rajendran Texas A&M
    • Sanjay Rekhi NIST
    • Ahmad-Reza Sadeghi TU Darmstadt

  • The 8th Workshop on Top Picks in Hardware and Embedded Security

    Over the past two decades, research in hardware and embedded security has yielded thousands of papers and more than a dozen high quality conferences and workshops dedicated to hardware security. Many of the techniques are being adopted by industry, (e.g., side-channel resistance techniques). Many have led to interesting intellectual contributions which impact go beyond hardware research community (e.g, physical-unclonable functions). The first workshop on Top Picks in Hardware and Embedded Security (Top Picks) was founded and co-located with ICCAD in 2018 to highlight the works that have made the greatest intellectual contributions. Since then, we have organized this workshop annually and co-located with ICCAD including the years when ICCAD was held virtually or abroad. We would like to continue this tradition by proposing Top Picks 2026.

    Papers that appeared in the leading security conference in the past six years will be invited to submit. A 2-page self-nomination letter is required to summarize key ideas and contributions of the paper, state the impacts that the paper has already made, and articulate how it will continue to influence the research community and industry.

    A program committee will review these submissions and select 10-15 papers for oral presentations. We require the presenters to be an senior author/co-author to enable a high quality presentation and discussion session after the presentation.

    After the workshop, an ad hoc committee from the program committee and senior attendees of the workshop will choose 4-8 winners of Top Picks. The winners will be invited to contribute to a special issue in IEEE Design & Test magazine.

    The co-founder of Top Picks workshop are:

    • Ramesh Karri, New York University

    • Gang Qu, University of Maryland College Park

    • Jeyavijayan (JV) Rajendran, Texas A&M University

    • Ahmad-Reza Sadeghi, TU Darmstadt

    • Shuwen Deng Tsinghua University
    • Gang Qu University of Maryland