Chip technology underpins progress across sectors such as automotive, telecommunications, finance, and healthcare. However, continued improvements in performance, efficiency, and functionality are increasingly constrained by the limits of traditional CMOS scaling and TSV-based 3D integration, challenged by scaling, memory, power, sustainability, and cost. Increasing integration density has long been a key enabler of progress in logic design. However, conventional two-dimensional CMOS scaling faces fundamental physical and economic challenges. Expanding integration into the third dimension offers a natural path forward. 3D Nanofabric introduces a disruptive alternative by enabling the simultaneous processing of N identical stacked layers, independent of the number of layers. This unique capability dramatically reduces fabrication cost and hardware footprint while unlocking new possibilities for dense, energy-efficient, and high-performance systems. This new fabrication paradigm has profound implications across the entire semiconductor design stack—from process design kits (PDKs) and physical design methodologies to logic and system architecture. Traditional EDA tools must evolve to address these cross-layer co-design challenges and opportunities. This session will bring together experts across the full design stack, spanning technology, design automation, and system architecture, to discuss the methodologies and innovations required to realize the full potential of 3D Nanofabric and shape the next era of semiconductor design. As this session covers the technology and the entire design stack, from EDA, circuit design, memory, and system architecture, it should be relevant to a large audience at ICCAD from both academia and industry.
