Keynote Speakers

Artificial intelligence is beginning to transform computing at both ends of the design process: it is changing how we design chips, and it is changing the kinds of chips and systems we need to build. AI-assisted and agentic design methodologies promise to compress development cycles, expand architectural exploration, and automate increasingly complex tasks across design exploration, specification, RTL generation, verification, physical design, and system optimization. At the same time, rapidly evolving model architectures, inference workloads, and agentic applications are creating new requirements for latency, interactivity, energy efficiency, cost per token, memory systems, and programmability.

This talk will explore what comes next when hardware, software, and AI models are no longer optimized independently. Future systems will increasingly require continuous co-design across models, algorithms, architectures, packaging, interconnects, and software, with AI participating directly in the optimization loop. Open-weight models and enterprise-controlled AI platforms may further shift where innovation occurs and who controls data, deployment, and inference economics. Looking beyond today’s data center, physical AI and emerging world-action models will introduce stringent real-time and energy constraints, while hybrid AI, HPC, and quantum systems may open new paths for scientific discovery. The central question for the design community is therefore broader than how AI can improve CAD: what happens when AI becomes both a workload we design for and an active participant in designing the next generation of computing systems?

To meet the stringent energy-efficiency and performance needs of deep learning workloads, minimizing data movement is crucial. This trend plays to the strengths of spatial architectures, including not only FPGAs but also processor arrays with mesh interconnects like the Cerebras Wafer Scale Engine and AMD AI Engine arrays. Spatial architectures also have characteristics that make them particularly well-suited to More-than-Moore integration that stacks multiple dice, connects them with interposers, or leverages wafer-scale integration. To explore this broad architecture space, we need flexible tools that can exploit the features of devices ranging from new FPGAs to novel spatial processor arrays. In this talk, I will discuss the strengths of these spatial platforms across a range of deep learning applications, outline how the different platforms are exploiting More-than-Moore integration, and give an overview of the tools we are creating to help enable and explore 3D FPGAs, new embedded FPGAs, and spatial processor arrays.