AI-era systems increasingly rely on chiplets, advanced packaging, and 3D stacking, where power delivery, transient droop, and reliability must be managed across die boundaries and design hierarchies. A key bottleneck in scaling power integrity for such systems is the lack of a consistent abstraction and data exchange model that connects early power modeling to signoff-level IR-drop and reliability analysis. While standardized multi-level power modeling abstractions (e.g., IEEE 2416) enable architectural exploration, signoff IR-drop and electromigration data remain locked in tool-specific representations (e.g., XPGV, ROM), making correlation, reuse, and hierarchical integration difficult. This disconnect increasingly leads to late-stage correlation gaps, conservative guard-bands, and limited reuse across design hierarchies. This session presents a unified technical pipeline spanning abstraction-level modeling, hierarchical power-grid analysis (PGA), and multi-die power delivery. It begins by examining how power-model fidelity evolves across abstraction levels and how mismatches propagate into IR-drop sensitivity, timing margins, and reliability outcomes. It then introduces scalable hierarchical PGA methods that preserve signoff fidelity from IP to SoC. Extending into 3D-IC systems, the session addresses vertical PDN challenges including TSV/microbump interfaces, inter-die coupling, and thermally amplified droop. The session is structured to explicitly connect early modeling choices to downstream physical effects. Each talk presents concrete methodologies, measurable correlation insights, and practical guidance for integrating modeling, analysis, and validation across the design stack. Together, the session highlights where fidelity is lost across abstraction levels and how it can be recovered through improved modeling, aggregation, and validation. Unlike prior efforts that treat modeling, IR-drop, and packaging independently, this session focuses on their coupling across abstraction levels, hierarchy, and multi-die integration. A cross-vendor panel will debate whether the field should converge toward a hierarchical IR-drop data exchange layer or continue with tool-specific ecosystems augmented by adapters, considering fidelity, scalability, and IP protection. The timing is driven by industry shifts toward chiplets, 3D-IC integration, and early-stage power-driven design. Without a consistent methodology, teams face late-stage surprises, over-conservative guard-bands, and limited reuse across hierarchies. This session addresses that gap with both practical methods and a forward-looking path toward interoperable design flows.
