The explosive growth of large language models (LLMs) is reshaping modern computing, driving unprecedented demands on performance, energy efficiency, scalability, and reliability. At the same time, the emergence of 2.5D and 3D heterogeneous, chiplet-based multi-die architectures is redefining the hardware substrate for next-generation systems. While these architectures offer a compelling path forward, they also introduce significant challenges, including cross-die communication bottlenecks, thermal coupling, process variability, and increased susceptibility to reliability and security threats. This special session focuses on the design of multi-chip systems that can efficiently and robustly support LLM workloads. It explores cross-layer EDA and co-design strategies for heterogeneous architectures that integrate compute, memory, and interconnect fabrics to meet the unique computational and data-movement characteristics of LLMs. By bringing together experts in EDA, testing, and hardware security, the session highlights emerging methodologies that span device, architecture, and system levels. It will examine how architectural heterogeneity and advanced integration technologies can be harnessed to deliver scalable performance, while addressing critical concerns such as testability, fault tolerance, and security in complex multi-die systems. Through this perspective, the session aims to advance a holistic vision for reliable, secure, and high-performance multi-chip computing platforms tailored for the demands of AI workloads.
