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GenAI for Chip Design Across the Lifecycle: Design, Optimization, Security, and Reliability

AI-driven methodologies are rapidly transforming the design of next-generation integrated circuits, enabling new levels of automation, adaptability, and intelligence across the chip design lifecycle. As this paradigm accelerates, it exposes complex challenges in chip design spanning design, optimization, security, and reliability that AI-driven methodologies aim to address. Addressing these challenges is essential to unlock the full potential of scalable and robust design flows for emerging domains such as AI acceleration, large-scale inference, and high-performance computing. In this proposed special session, we bring together leading experts to explore cutting-edge advances in self-evolving optimization agents, automated physical design frameworks, AI-guided hardware security testing, and cross-stage reasoning for silicon quality improvement. The session aims to synthesize insights from both academia and industry, highlight opportunities for end-to-end AI integration across the design stack, and chart a forward-looking roadmap for building intelligent, reliable, and high-performance chip design systems at scale.