2021 International Conference On
Computer-Aided Design


The Premier Conference Devoted to Technical Innovations in
Electronic Design Automation
Virtual Technical Program:
November 1-4, 2021
Networking In-Person:
November 5, 2021



On Thursday, we offer you five interesting workshops (plus another two which are co-located to ICCAD) - covering a huge range of topics and taking both, academic as well as industrial, perspectives. As a special feature: You only need to register for workshops once, and can participate/switch between all those workshops (except for the both co-located ones).

Note Agenda time zone is UTC-7 / PDT (CALIFORNIA)
November 04, 2021: 8:00 am – 12:40 pm - November 05, 2021: 8:00 am – 12:00 pm

Ibrahim (Abe) Elfadel - Khalifa University, UAE
Subhasish Mitra - Stanford University, USA

This is the 3rd version of a trending workshop whose goal is to provide a forum to present and discuss the current trends in computer-aided design in support of domain-specific accelerator chips, especially for artificial intelligence and machine learning applications. The workshop will be concerned with the VLSI methodology flow from high-level synthesis to physical verification and performance prediction, particularly in the way it gets impacted with the emerging design paradigms of domain-specific instruction sets, approximate computing, inmemory computing, and stochastic computing. Of particular interest to the workshop are the transformations that VLSI CAD has to undergo to adapt to the post-CMOS technologies when they are considered in the context of accelerator design. The workshop will include, but will not be limited to, the following topics:
  • High-level synthesis of machine-learning accelerators
  • Design space exploration of domain-specific accelerators
  • Tools and methodologies for in-memory computing
  • Tools and methodologies for approximate computing
  • CAD for emerging accelerator technologies: ReRAM, MRAM, Photonics, etc.
  • Tools and methodologies for the post-CNN era
  • Tools and methodologies for the testing and verification of accelerator chip

November 04, 2021: 07:20 am - 12:30 pm

Alberto Bosio - École Centrale de Lyon, FR
Alexandra Kourfali - University of Stuttgart, GER
Alessandro Savino - Politecnico di Torino, IT
Jürgen Teich - Friedrich-Alexander Universität Erlangen-Nürnberg (FAU), GER

This workshop aims at exploring the Approximate Computing (AxC) continuum, making room for the exploration of methodologies able to exploit effective and real systems that can inspire applications in many recent application domains such as machine learning, safety, and security. AxC is defined based on the intuitive observation that, while performing exact computation requires a high amount of computational resources, allowing a selective approximation or an occasional relaxation of the specification may provide significant gains in energy efficiency while still providing acceptable results. Nowadays, AxC represents a novel design paradigm for building modern systems, which offer efficiency trade-offs, between performance, power consumption, hardware area, execution timing, and the quality/exactness of the outcomes.

AxC 2021 Tentative Program
07:20 - 07:30 amOpening (Welcome Message from Chairs)
07:30 - 09:50 amInvited Talk Session
07:30 - 08:10 amApproximate Computing for Low Power Circuits and Systems
Weiqiang Liu - Nanjing University of Aeronautics and Astronautics
08:10 - 08:20 amBreak
08:20 - 09:00 am Automated and Sound Approximation of Numerical Kernels
Eva Darulova - Max Planck Institute for Software Systems (MPI-SWS)
09:10 - 09:50 am Approximate Computing – The Holy Grail of Low-Energy Electronic Systems?
Jari Nurmi - Tampere University
09:50 - 10:00 amBreak
10:00 - 11:00 amRegular Session 1 | Approximate computing in Machine Learning and DSP Applications
10:00-10:20 amNeural Network Hardware Acceleration Based on Hybrid Approximate Multipliers
Siyuan Liang, Ke Chen, Pengfei Huang, Peipei Yin and Weiqiang Liu
10:20-10:40 amCNN Compression through Retraining-free Weight Sharing
Etienne Dupuis, David Novo, Ian O'Connor and Alberto Bosio
10:40-11:00 am Combining Logic Refactoring and Approximate Computing to Power- and Area-Efficient Gaussian Filter Designs
Marcio Monteiro, Ismael Seidel, Mateus Grellert, Jose Luis Güntzel, Leonardo Soares and Cristina Meinhardt
11:00 - 11:10 amBreak
11:10 am - 12:10 pmRegular Session 2 | Approximate Design Techniques
11:10-11:30 amApproximate PIM: An IMPLY-based Approximate Adder
Seyed Erfan Fatemieh, Mohammad Reza Reshadinezhad and Nima Taherinejad
11:30 – 11:50 amAssertion-aware based approximate computing
Moreno Bragaglio, Samuele Mori, Samuele Germiniani, Alberto Bosio, Marcello Traiola and Graziano Pravadelli
11:50 am – 12:10 amTask Scheduling on Mixed-Precision MPSoC
Ahmad Sadigh Baroughi, Stefan Huemer, Hadi Shahriar Shahhoseini and Nima Taherinejad
12:10 - 12:20 pmBreak
12:20 - 01:20 pmRegular Session 3 | Approximate Synthesis for FPGA targets
12:20 – 12:40 pmApproximation Space Exploration for FPGA Accelerators Using Fault Injection
Ioannis Tsounis, Athanasios Papadimitriou and Mihalis Psarakis
12:40 – 13:00 pmExploring a Decision Tree Synthesis Flow for Approximate Circuits
Brunno Abreu, Jonata Carvalho, Mateus Grellert and Cristina Meinhardt
13:00 – 13:20 pmA Catalog-based AIG-Rewriting Approach to the Design of Approximate Components
Mario Barbareschi, Salvatore Barone, Nicola Mazzocca and Alberto Moriconi
13:20 - 13:30 pmClosing Session


November 04, 2021: 8:20 am – 01:05 pm

Yingyan (Celine) Lin - Rice University, USA
Yanzhi Wang - Northeastern University, USA

In recent years, machine/deep learning algorithms has unprecedentedly improved the accuracies in practical recognition and classification tasks, some even surpassing human-level accuracy. While significant progresses have been made on accelerating the models for real-time inference on edge and mobile devices, the training of the models largely remains offline on server side. State-of-theart learning algorithms for deep neural networks (DNN) imposes significant challenges for hardware implementations in terms of computation, memory, and communication. This is especially true for edge devices and portable hardware applications, such as smartphones, machine translation devices, and smart wearable devices, where severe constraints exist in performance, power, and area.
There is a timely need to map the latest complex learning algorithms to custom hardware, in order to achieve orders of magnitude improvement in performance, energy efficiency and compactness. Exemplary efforts from industry and academia include many application-specific hardware designs (e.g., xPU, FPGA, ASIC, etc.). Recent progress in computational neurosciences and nanoelectronic technology, such as emerging memory devices, will further help shed light on future hardwaresoftware platforms for learning on-a-chip. At the same time new learning algorithms need to be developed to fully explore the potential of the hardware architecture.
The overarching goal of this workshop is to explore the potential of on-chip machine learning, to reveal emerging algorithms and design needs, and to promote novel applications for learning. It aims to establish a forum to discuss the current practices, as well as future research needs in the aforementioned fields.

11:00am - 11:05amOpening and Introduction
11:05am - 11:50amKeynote Talk 1
Session Chair: Yingyan (Celine) Lin, Rice University
Light in AI: Toward Efficient and Robust Neurocomputing with Optical Neural Networks
David Pan, The University of Texas at Austin
11:50am - 1:05pmSession 1: Session Chair: Yingyan (Celine) Lin, Rice University
Session Chair: Yingyan (Celine) Lin, Rice University
11:50am - 12:15pmEfficient Audio-Visual Understanding on AR Devices
Meng Li, Facebook
12:15pm - 12:40pmPrivacy in Federated Learning at Scale
Peter Kairouz, Google
12:40pm - 1:05pmCo-Design for Low-Bitwidth Neural Networks with Dynamic Quantization
Zhiru Zhang, Cornell University
1:05pm - 1:25pmBreak
1:25pm - 2:40pmSession 2: Hardware-award Deep Learning Techniques
Session Chair: Yingyan (Celine) Lin, Rice University
1:25pm - 1:50pmThe Lottery Ticket Hypothesis: On Sparse, Trainable Neural Networks
Jonathan Frankle, Massachusetts Institute of Technology
1:50pm - 2:15pmIntelligent Visual Computing
Yuhao Zhu, University of Rochester
2:15pm - 2:40pmAlgorithm and Hardware Co-Design for Efficient Deep Learning: Sparse and Low-rank Perspectives
Bo Yuan, Rugster University
2:40pm - 3:25pmKeynote Talk 2
Session Chair: Yanzhi Wang, Northeastern University
Democratizing TinyML: Generalization, Standardization and Automation
Vijay Janapa Reddi, Harvard University
3:30pm - 4:45pmSession 3: Emerging Device and Neuromorphic Computing
Session Chair: Yanzhi Wang, Northeastern University
3:30pm - 3:55pmNeuroSim Benchmark Framework
Shimeng Yu, Georgia Institute of Technology
3:55pm - 4:20pmMemristive devices and arrays for computing
Jianhua Yoshua Yang, University of Southern California
4:20pm - 4:45pmSecure and Efficient Deep Learning Computing-in-Memory, A Software and Hardware Co-Design Perspective
Deliang Fan, Arizona State University

November 04, 2021: 07:20 am - 01:30 pm

Gang Qu - University of Maryland
Johanna Sepulveda - Airbus Defence and Space

Top Picks Workshop creates a venue to showcase the best and high impact recently published works in the area of hardware and embedded security. These works will be selected from conference papers that have appeared in leading hardware security conferences including but not limited to DAC, ICCAD, DATE, ASPDAC, HOST, Asian HOST, GLSVLSI, VLSI Design, CHES, ETS, VTS, ITC, S&P, Usenix Security, CCS, NDSS, ISCA, MICRO, ASPLOS, HPCA, HASP, ACSAC, Euro S&P, and Asia CCS.

7:20 am – 7:30 amWelcome message from the chair
Gang Qu
7:30 am – 8:30 amSession 1 Logic Locking
Chair: Gang Qu, University of Maryland

Provably-Secure Logic Locking: From Theory to Practice
Authors: Muhammad Yasin, Abhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf, Jeyavijayan Rajendran and Ozgur Sinanoglu
Speaker: Prof. Jeyavijayan Rajendran

Pirates of the Carry-Boolean: Exploring Structural Artifacts of Logic Locking with SAIL
Authors: Prabuddha Chakraborty, Jonathan Cruz, Abdulrahman Alaql and Swarup Bhunii
Speaker: Prabuddha Chakraborty
8:30 am – 9:30 amSession 2 Trust Execution Environment
Chair: Nader Sehatbaksh, University of California, Los Angeles

SANCTUARY: ARMing TrustZone with User-space Enclaves
Authors: Emmanuel Stapf, Ferdinand Brasser, David Gens, Patrick Jauernig and Ahmad-Reza Sadeghi
Speaker: Emmanuel Stapf

HybCache: Hybrid Side-Channel-Resilient Caches for Trusted Execution Environments
Authors: Ghada Dessouky, Tommaso Frassetto and Ahmad-Reza Sadeghi
Speaker: Tommaso Frassetto
9:30 am – 10:30 amSession 3 Side-Channel Analysis
Chair: Ian Harris, University of California, Irvine

The Curse of Class Imbalance and Conflicting Metrics with Machine Learning for Side-channel Evaluations
Authors: Stjepan Picek, Annelie Heuser, Alan Jovic, Shivam Bhasin and Francesco Regazzoni
Speaker: Dr. Stjepan Picek

Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange Protocols
Authors: Aydin Aysu, Youssef Tobah, Mohit Tiwari, Andreas Gerstlauer and Michael Orshansky
Speaker: Prof. Aydin Aysu
10:30 am – 10:45 ambreak
10:45 am – 11:45 amSession 4 Identification: from Recycled IC to DNN
Chair: Yingjie Lao, Clemson University

Recycled IC Detection Based on Statistical Methods
Authors: Ke Huang, Yu Liu, Nenad Korolija, John Carulli and Yiorgos Makris
Speaker: Prof. Yiorgos Makris

DeepAttest: An End-to-End Attestation Framework for Deep Neural Networks
Authors: Huili Chen, Cheng Fu, Bita Darvish Rouhani, Jishen Zhao and Farinaz Koushanfar
Speaker: Huili Chen
11:45 am – 1:15 pmSession 5 Buffer Exploitation and Memory Safety
Chair: Jiafeng Xie, Villanova University

SpectreRSB: Spectre attacks using the return stack buffer
Authors: Esmaeil Mohammadian Koruyeh, Khaled Khaswaneh, Chengyue Song and Nael Abu-Ghazaleh
Speaker: Prof. Nael Abu-Ghazaleh

Secure TLBs
Authors: Shuwen Deng, Wenjie Xiong and Jakub Szefer
Speaker: Shuwen Deng

CHEx86: Context-Sensitive Enforcement of Memory Safety via Microcode-Enabled Capabilities
Authors: Rasool Sharifi and Ashish Venkat
Speaker: Rasool Sharifi
1:15 pm – 1:30 pmclosing remarks
Johanna Sepulveda


November 04, 2021: 07:20 am - 01:30 pm

Diana Göhringer - TU Dresden, GER
Anton Klotz - Cadence Design Systems, GER
Mark Willoughby - Europractice, UK
Christian Sauer - Cadence Design Systems, GER

The workshop targets an academic and industrial audience interested in a practical introduction to shift-left methodologies and their link to the traditional SoC implementation flow. Using Cadence technologies for virtual prototyping, the creation of extensible processors (Tensilica), and the synthesis of hardware from high-level SystemC descriptions (Stratus), participants learn how to develop efficient SoCs for IoT and Edge applications by using hardware acceleration. Besides an introduction to edge and IoT application domains and theoretical background on different hardware acceleration options the workshop includes hands-on sessions for the technologies and flows mentioned. Designs and tools are accessible via a cloud environment provided by Europractice. The overall idea is to take a compute intensive application and to show how the execution of the application can be optimized using different measures like additional processor instructions, optimized data transport and dedicated hardware accelerators. The main development work will be done using a virtual prototype written in SystemC. At the end of the development the design will be synthesized into hardware.

Please note that the Cadence workshop requires a separate registration, and in order to ensure proper support through the workshop, only a limited number of participants can attend. Please consider the workshop's website for more detailed information.

07:20 - 08:00 amOverview and introduction
Sarmad Dahir / Frederik Kautz
08:00 - 09:00 amEmbedded processors and tool chains with first Hands-on
Ernesto Cristopher Villegas / Muhammad Ali
09:15 – 10:15 amMapping, execution and measurement of applications with second Hands-On
Frederik Kautz/ Ernesto Cristopher Villegas
10:30 – 11:30 amBasic hardware accelerator with third Hands-On
Sarmad Dahir
11:45 am – 12:45 pmAccelerator design, integration and validation in SystemC with fourth Hand-On
Sarmad Dahir / Muhammad Ali
01:00 - 01:30 pmSummary
Sarmad Dahir

November 04, 2021: 10:00 am - 02:00 pm

Matthew Guthaus - University of California, USA
Jose Renau - University of California, USA

The WOSET workshop is co-located with ICCAD 2021 and aims to galvanize the open-source EDA movement. The workshop will bring together EDA researchers who are committed to open-source principles to share their experiences and coordinate efforts towards developing a reliable, fully open-source EDA flow. The workshop will feature presentations and posters that overview existing or under-development open-source tools, designs and technology libraries. A live demo session for tools in advanced state will be planned. The workshop will feature a panel on the present status and future challenges in open-source EDA, and how to coordinate efforts and ensure quality and interoperability across open-source tools. A cash award will be given for a Best Tool Award.

Please note that WOSET is a co-located workshop and requires a separate registration. Please consider WOSET’s website for more detailed information.


November 04, 2021: 07:00 am - 02:00 pm

Mustafa Badaroglu - Qualcomm, BE
Brian Cline - Arm, USA
Ismail Bustany - Xilinx, USA

The 23rd ACM/IEEE International Workshop on System-Level Interconnect Pathfinding (SLIP 2021), co-hosted with ICCAD 2021, will bring together researchers and practitioners who have a shared interest in the challenges and futures of system-level interconnect, coming from wide-ranging backgrounds that span system, application, design, and technology.

Please note that SLIP is a co-located workshop and requires a separate registration. Please consider SLIP’s website for more detailed information.