2021 International Conference On
Computer Aided Design


The Premier Conference Devoted to Technical Innovations in
Electronic Design Automation
Virtual Technical Program:
November 1-4, 2021
Networking In-Person:
November 5, 2021



On Thursday, we offer you six interesting workshops (plus another one which is co-located to ICCAD) -- covering a huge range of topics and taking both, academic as well as industrial, perspectives. As a special feature: You only need to register for workshops once, and can participate/switch between all those workshops (except for the co-located one).
Ibrahim (Abe) Elfadel - Khalifa University, UAE
Subhasish Mitra - Stanford University, USA

This is the 3rd version of a trending workshop whose goal is to provide a forum to present and discuss the current trends in computer-aided design in support of domain-specific accelerator chips, especially for artificial intelligence and machine learning applications. The workshop will be concerned with the VLSI methodology flow from high-level synthesis to physical verification and performance prediction, particularly in the way it gets impacted with the emerging design paradigms of domain-specific instruction sets, approximate computing, inmemory computing, and stochastic computing. Of particular interest to the workshop are the transformations that VLSI CAD has to undergo to adapt to the post-CMOS technologies when they are considered in the context of accelerator design. The workshop will include, but will not be limited to, the following topics:
  • High-level synthesis of machine-learning accelerators
  • Design space exploration of domain-specific accelerators
  • Tools and methodologies for in-memory computing
  • Tools and methodologies for approximate computing
  • CAD for emerging accelerator technologies: ReRAM, MRAM, Photonics, etc.
  • Tools and methodologies for the post-CNN era
  • Tools and methodologies for the testing and verification of accelerator chip

Alberto Bosio - École Centrale de Lyon, FR
Alexandra Kourfali - University of Stuttgart, GER
Alessandro Savino - Politecnico di Torino, IT
Jürgen Teich - Friedrich-Alexander Universität Erlangen-Nürnberg (FAU), GER

This workshop aims at exploring the Approximate Computing (AxC) continuum, making room for the exploration of methodologies able to exploit effective and real systems that can inspire applications in many recent application domains such as machine learning, safety, and security. AxC is defined based on the intuitive observation that, while performing exact computation requires a high amount of computational resources, allowing a selective approximation or an occasional relaxation of the specification may provide significant gains in energy efficiency while still providing acceptable results. Nowadays, AxC represents a novel design paradigm for building modern systems, which offer efficiency trade-offs, between performance, power consumption, hardware area, execution timing, and the quality/exactness of the outcomes.


Qinru Qiu - Syracuse University, USA
Yingyan Lin - Rice University, USA
Chenchen Liu - University of Maryland, USA

In recent years, machine/deep learning algorithms has unprecedentedly improved the accuracies in practical recognition and classification tasks, some even surpassing human-level accuracy. While significant progresses have been made on accelerating the models for real-time inference on edge and mobile devices, the training of the models largely remains offline on server side. State-of-theart learning algorithms for deep neural networks (DNN) imposes significant challenges for hardware implementations in terms of computation, memory, and communication. This is especially true for edge devices and portable hardware applications, such as smartphones, machine translation devices, and smart wearable devices, where severe constraints exist in performance, power, and area.
There is a timely need to map the latest complex learning algorithms to custom hardware, in order to achieve orders of magnitude improvement in performance, energy efficiency and compactness. Exemplary efforts from industry and academia include many application-specific hardware designs (e.g., xPU, FPGA, ASIC, etc.). Recent progress in computational neurosciences and nanoelectronic technology, such as emerging memory devices, will further help shed light on future hardwaresoftware platforms for learning on-a-chip. At the same time new learning algorithms need to be developed to fully explore the potential of the hardware architecture.
The overarching goal of this workshop is to explore the potential of on-chip machine learning, to reveal emerging algorithms and design needs, and to promote novel applications for learning. It aims to establish a forum to discuss the current practices, as well as future research needs in the aforementioned fields.


Gang Qu - University of Maryland, USA
Johanna Sepulveda - Airbus Defence and Space, GER

Top Picks Workshop creates a venue to showcase the best and high impact recently published works in the area of hardware and embedded security. These works will be selected from conference papers that have appeared in leading hardware security conferences including but not limited to DAC, ICCAD, DATE, ASPDAC, HOST, Asian HOST, GLSVLSI, VLSI Design, CHES, ETS, VTS, ITC, S&P, Usenix Security, CCS, NDSS, ISCA, MICRO, ASPLOS, HPCA, HASP, ACSAC, Euro S&P, and Asia CCS.


Matthew Guthaus - University of California, USA
Jose Renau - University of California, USA

The WOSET workshop aims to galvanize the open-source EDA movement. The workshop will bring together EDA researchers who are committed to open-source principles to share their experiences and coordinate efforts towards developing a reliable, fully open-source EDA flow. The workshop will feature presentations and posters that overview existing or under-development open-source tools, designs and technology libraries. A live demo session for tools in advanced state will be planned. The workshop will feature a panel on the present status and future challenges in open-source EDA, and how to coordinate efforts and ensure quality and interoperability across open-source tools. A cash award will be given for a Best Tool Award.


Diana Göhringer - TU Dresden, GER
Anton Klotz - Cadence Design Systems, GER
Mark Willoughby - Europractice, UK
Christian Sauer - Cadence Design Systems, GER

The workshop targets an academic and industrial audience interested in a practical introduction to shift-left methodologies and their link to the traditional SoC implementation flow. Using Cadence technologies for virtual prototyping, the creation of extensible processors (Tensilica), and the synthesis of hardware from high-level SystemC descriptions (Stratus), participants learn how to develop efficient SoCs for IoT and Edge applications by using hardware acceleration. Besides an introduction to edge and IoT application domains and theoretical background on different hardware acceleration options the workshop includes hands-on sessions for the technologies and flows mentioned. Designs and tools are accessible via a cloud environment provided by Europractice. The overall idea is to take a compute intensive application and to show how the execution of the application can be optimized using different measures like additional processor instructions, optimized data transport and dedicated hardware accelerators. The main development work will be done using a virtual prototype written in SystemC. At the end of the development the design will be synthesized into hardware.

Mustafa Badaroglu - Qualcomm, BE
Brian Cline - Arm, USA
Ismail Bustany - Xilinx, USA

The 23rd ACM/IEEE International Workshop on System-Level Interconnect Pathfinding (SLIP 2021), co-hosted with ICCAD 2021, will bring together researchers and practitioners who have a shared interest in the challenges and futures of system-level interconnect, coming from wide-ranging backgrounds that span system, application, design, and technology.

Please note that SLIP is a co-located workshop and requires a separate registration. Please consider SLIP’s website for more detailed information.