2020 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 2-5, 2020VIRTUAL CONFERENCE

CONGRATULATIONS TO THE 2020 ACCEPTED PAPERS!

 

Paper ID Paper Title
14 Dynamic Minimization of Bi-Kronecker Functional Decision Diagrams
16 ECC Cache: A Lightweight Error Detection for Phase-Change Memory Stuck-At Faults
21 Laser Attack Benchmark Suite
30 fuseGNN: Accelerating Graph Convolutional Neural Network Training on GPGPU
31 GA-Mapper: Automating the HW Mapping of DNN Models onAccelerators via Genetic Algorithm
35 Exploring Target Function Approximation for Stochastic Circuit Minimization
37 ReTransformer: ReRAM-based Processing-in-Memory Architecture for Transformer Acceleration
38 Optimizing Physical Layout of Wavelength-Routed ONoCs for Laser Power Reduction
44 Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling
46 Leveraging Weakly-hard Constraints for Improving System Fault Tolerance with Functional and Timing Guarantees
48 AxHLS: Design Space Exploration and High-Level Synthesis of Approximate Accelerators using Approximate Functional Units and Analytical Models
49 Aadam: A Fast, Accurate, and Versatile Aging-Aware Cell Library Delay Model using Feed-Forward Neural Network
60 HyperTune: Dynamic Hyperparameter Tuning For Efficient Distribution of DNN Training Over Heterogeneous Systems
68 Electromigration Immortality Check considering Joule Heating Effect for Multisegment Wires
70 CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit
75 Optimal Layout Synthesis for Quantum Computing
77 Retiming for High-performance Superconductive Circuits with Register Energy Minimization
80 Routing-Free Crosstalk Prediction
81 Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization
82 iTPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis
89 ABACUS: Address-partitioned Bloom filter on Address Checking for UniquenesS in IoT Blockchain
107 Power Distribution Network Generation for Optimizing IR-Drop Aware Timing
111 VLSI Placement Parameter Optimization using Deep Reinforcement Learning
113 Energy-Efficient Control Adaptation with Safety Guarantees for Learning-Enabled Cyber-Physical Systems
114 Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits
116 CLEANN: Accelerated Trojan Shield for Embedded Neural Networks
122 CCCS: Customized SPICE-level Crossbar-array circuit Simulator for In-Memory Computing
125 Optimally Approximated and Unbiased Floating-Point Multiplier with Runtime Configurability
128 CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation
131 THRIFTY: Training with Hyperdimensional Computing across Flash Hierarchy
132 Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing
134 GPU-Accelerated Static Timing Analysis
139 DRAMA: An Approximate DRAM Architecture for High-performance and Energy-efficient Deep Training System
141 A Customized Graph Neural Network Model for Guiding Analog IC Placement
144 MLCache: A Space-Efficient Cache Scheme based on Reuse Distance and Machine Learning for NVMe SSDs
146 Encoding, Model, and Architecture: Systematic Optimization for Spiking Neural Network in FPGAs
149 Dali: A Gridded Cell Placement Flow
151 SWIPE: Enhancing Robustness of ReRAM Crossbars for In-memory Computing
162 HitM: High-Throughput ReRAM-based PIM for Multi-Modal Neural Networks
164 A Non-Gaussian Adaptive Importance Sampling Method for High-Dimensional and Multi-Failure-Region Yield Analysis
167 GridNet: Fast Data-Driven EM-Induced IR Drop Prediction and Localized Fixing for On-Chip Power Grid Networks
170 PROS: a Plug-in for Routability Optimization applied in the State-of-the-art Commercial EDA Tool Using Deep Learning
179 Dual-Output LUT Merging during FPGA Technology Mapping
184 Faultless to a Fault? The Case of Threshold Implementations of Crypto-systems vs Fault Template Attacks
189 Automated Synthesis of Custom Networks-on-Chip for Real-World-Applications
191 HAPI: Hardware-Aware Progressive Inference
192 A Monte Carlo Tree Search Framework for Quantum Circuit Transformation
199 Thermal-aware Optimization Framework for ReRAM-based Deep Neural Network Acceleration
206 DAMO: Deep Agile Mask Optimization for Full Chip Scale
211 XOR-CIM: Compute-in-Memory SRAM Architecture with Embedded XOR Encryption
223 Multi-Electrostatics Based Robust VLSI Placement with Region Constraints
224 NEST: DIMM based Near-Data-Processing Accelerator for k-mer Counting
231 DISQ: A Novel Quantum Output State Classification Method on IBM Quantum Computers using OpenPulse
234 F2VD: Fluid Rates to Virtual Deadlines for Precise Mixed-Criticality Scheduling on a Varying-Speed Processor
248 SETGAN: Scale and Energy Trade-off GANs for Image Applications on Mobile Platforms
249 A Crowd-Based Explosive Detection System with Two-Level Feedback Sensor Calibration
256 NeuroMAX: A High Throughput, Multi-Threaded, Log-Based Accelerator for Convolutional Neural Networks
263 On Uniformly Sampling Traces of a Transition System
272 SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs
274 DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator
275 SF-GRASS: Solver-Free Graph Spectral Sparsification
278 Electromigration Checking Using a Stochastic Effective Current Model
281 Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs
288 Effective Analog-Mixed-Signal Circuit Placement Considering System Signal Flow
293 Automatic-SSD: Full Hardware Automation over New Memory for High Performance and Energy Efficient PCIe Storage Cards
295 BoMaNet: Boolean Masking of an Entire Neural Network
298 Information Leakage from FPGA Routing and Logic Elements
299 MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital-Analog Nonvolatile Processing-In-Memory Block
308 Hotspot Detection via Attention-based Deep Layout Metric Learning
309 Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process
317 Just Say Zero: Containing Critical Bit-Error Propagation in Deep Neural Networks With Anomalous Feature Suppression
320 Meshed Stack Via Design Considering Complicated Design Rules with Automatic Constraint Generation
334 Optimizing Stochastic Computing for Low Latency Inference of Convolutional Neural Networks
338 A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT
342 Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution Regularization
348 Placing DNNs on Wafer-Scale AI Accelerator with Optimal Kernel Sizing
349 PathDriver: A Path-Driven Architectural Synthesis Flow for Continuous-Flow Microfluidic Biochips
354 RIMI: Instruction-level Memory Isolation for Embedded Systems on RISC-V
360 Layout Pattern Generation and Legalization with Generative Learning Models
365 Fixed-Priority Scheduling and Controller Co-Design for Time-Sensitive Networks
373 Countering Variations and Thermal Effects for Accurate Optical Neural Networks
375 COALA: Concurrently Assigning Wire Segments to Layers for 2D Global Routing
387 LegoGNN: An Automated Framework for Generating FPGA-based Graph Learning Accelerators
389 Considering Decoherence Errors in the Simulation of Quantum Circuits Using Decision Diagrams
392 An Energy-Efficient Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning
393 Unlocking Wordline-level Parallelism for Fast Inference on RRAM-based DNN Accelerator
395 An Algorithm for Rule-based Layout Pattern Matching
401 Cell Library Characterization using Machine Learning for Design Technology Co-Optimization
402 A general approach for identifying hierarchical symmetry constraints for analog circuit layout
411 Test Generation using Reinforcement Learning for Delay-based Side Channel Analysis
417 DP-MAP: Towards Resistive Dot-Product Engines with Improved Precision
425 Efficient Hardware-Software Co-Design for Post-Quantum Crypto Algorithm SIKE on ARM and RISC-V based Microcontrollers
430 NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks
434 HyperFuzzing for SoC Security Specification
441 Dynamic IR-Drop ECO Optimization by Cell Movement with Staggering Current Waveforms and Machine Learning Guidance
444 A CAD-based methodology to optimize HLS code via the Roofline model
446 Practical Multi-armed Bandits in Boolean Optimization
473 ASAP: An Analytical Strategy for AQFP Placement
476 PUF-G: A CAD Framework for Automated Assessment of Provable Learnability from Formal PUF Representations
487 Symbolic Uniform Sampling with XOR Circuits
495 Power side channel attack analysis and detection
501 Mining Biochemical Circuits from Enzyme Databases via Boolean Reasoning
509 Routability-Driven Pin-Access Optimization for Monolithic 3D IC Designs
511 Hessian-Driven Unequal Parameter Protection for Robust DNN Inference
518 The Safe and Effective Application of Probabilistic Techniques in Safety-Critical Systems
526 A Quantitative Defense Framework against Power Attacks onMulti-tenant FPGA
529 Early-stage Automated Accelerator Identification Tool for Embedded Systems with Limited Area
539 Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs
541 Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-Design
549 Bayesian Accuracy Analysis of Stochastic Circuits
555 Modeling Techniques for Logic Locking
565 Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping
568 InterLock: An Intercorrelated Logic and Routing Locking
570 NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures
572 A Fast Learning-Driven Signoff Power Optimization Framework
581 Detection through Deep Neural Networks: A Reservoir Computing Approach for MIMO-OFDM Symbol Detection
587 FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory
602 Accelerating 3D Vertical Resistive Memories with Opportunistic Write Latency Reduction
604 Accurate Operation Delay Prediction for High-Level Synthesis with Graph Neural Networks
622 Hybrid-Shield: Accurate and Efficient Cross-Layer Countermeasure for Run-Time Detection and Mitigation of Cache-Based Side-Channel Attacks
624 Adaptable and Divergent Synthetic Benchmark Generation for Hardware Security
625 A Lightweight Approach to Detect Malicious-Unexpected Changes in the Error Rates of NISQ Computers
646 Word Level Property Directed Reachability
652 Concurrent Weight Encoding-based Detection for Bit-Flip Attack on Neural Network Accelerators
658 Performance Analysis of Priority-Aware NoCs with Deflection Routing under Traffic Congestion
665 SynergicLearning: Neural Network-based Feature Extraction for Highly-Accurate Hyperdimensional Learning
666 IoT-CAD: Context-Aware Adaptive Anomaly Detection in IoT through Sensor Association