2020 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 2-5, 2020VIRTUAL CONFERENCE

MP Associates, Inc.
WEDNESDAY November 04, 7:00am - 8:00am | Slot 5
EDA for More-Moore and More-than-Moore Designs: Challenges and Opportunities
Yao-Wen Chang - National Taiwan Univ.
As the process technology approaches the physics limit, the semiconductor industry faces severe manufacturing and design challenges.  Though at a slower pace than ever before, on one hand, Moore’s Law continues to push the limits of process lithography into the deep nanometer regime for better area, performance, and power.  On the other hand, More-than-Moore technologies add diverse devices and adopt 2.5D/3D heterogeneous integration to achieve better system-level power-performance-cost tradeoffs and higher design functionality.  In this talk, we investigate most expected More-Moore patterning, interconnect, and transistor technologies and More-than-Moore system-level heterogeneous integration, address their implications and challenges for advanced circuit and system implementations, highlight current EDA solutions, and suggest future research opportunities for these emerging challenges from the perspectives of technology, heterogeneity, scalability, and multi-objective requirements. 

Biography: Yao-Wen Chang received the B.S. degree from National Taiwan University (NTU) in 1988, and the M.S. and Ph.D. degrees from the University of Texas at Austin in 1993 and 1996, respectively, all in computer science. He is currently Distinguished Professor and the Dean of the College of Electrical Engineering and Computer Science, NTU. His current research interests lie in electronic design automation (EDA), with emphases on physical design and manufacturability. He has co-authored one textbook on EDA and another book on routing and over 320 ACM/IEEE conference/journal papers, including highly cited papers on floorplanning, placement, routing, manufacturability, and FPGA design. His NTUplace3 placer was transferred as the popular Custom Digital Placer of SpringSoft, acquired by the #1 EDA vendor, Synopsys, for US $400 million in 2012. His NTUplace4 is a 3-time champion from the DAC’12, ICCAD’13, and ISPD’15 placement contests, then the core engine of the MaxPlace placer, a leading placer of the Maxeda Technology co-founded by Dr. Chang in 2015. Dr. Chang received four awards at the 50th DAC in 2013 for the 1st Most Papers in DAC’s Fifth Decade (34 papers; #1 worldwide), etc. He is a winner of 21 top-3 place awards at ACM/IEEE EDA contests, 10 best paper awards (including DAC’17), and 23 best paper nominations from DAC (5 times), ICCAD (5 times), etc. He has received many research/teaching awards, such as the Distinguished Research Award from the Ministry of Science and Technology of Taiwan (three times, the limit), the IBM Faculty Awards (three times), and the MXIC Chair Professorship and two distinguished (highest honor) and nine excellent teaching awards from NTU.

Dr. Chang is an IEEE Fellow and currently the President of the IEEE CEDA. He has served on the editorial boards of IEEE TCAD, IEEE TVLSI, IEEE D&T, etc. He has also served as program/general chairs of ICCAD, program/general/steering committee chairs of ISPD, and program chairs of ASP-DAC and FPT. He has also served as an independent board director of Genesys Logic, a technical consultant of Faraday, MediaTek, and RealTek, and chair of the EDA Consortium of the MOE, Taiwan.