2019 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 4-7, 2019The Westin Westminster Westminster, CO

MP Associates, Inc.
THURSDAY November 07, 1:00pm - 6:00pm | Westminster I
EVENT TYPE: WORKSHOP
SESSION 3W
1st Workshop on Accelerator Computer-Aided Design

Speakers:
Yiran Chen - Duke Univ.
Priyanka Raina - Stanford Univ.
Stelios Diamantidis - Synopsys, Inc.
Victor Kravets - IBM Corp.
Danny Bankman - Stanford Univ.
Organizers:
Ibrahim Elfadel - Khalifa Univ.
Subhasish Mitra - Stanford Univ.

1. Topics This workshop provides a forum to present and discuss the current trends in computer-aided design in support of domain-specific accelerator chips, especially for artificial intelligence and machine learning applications. The workshop will be concerned with the VLSI methodology flow from high-level synthesis to physical verification and performance prediction, particularly in the way it gets impacted with the emerging design paradigms of domain-specific instruction sets, approximate computing, in-memory computing, and stochastic computing. Of particular interest to the workshop are the transformations that VLSI CAD has to undergo to adapt to the post-CMOS technologies when they are considered in the context of accelerator design. The workshop will include, but will not be limited to, the following topics: • High-level synthesis of machine-learning accelerators • Design space exploration of domain-specific accelerators • Tools and methodologies for in-memory computing • Tools and methodologies for approximate computing • CAD for emerging accelerator technologies: ReRAM, MRAM, Photonics, etc. • Tools and methodologies for the post-CNN era • Tools and methodologies for the testing and verification of accelerator chips. 2. Audience The workshop will be of interest to all designers and CAD engineers involved in accelerator projects or to academics and graduate students interested in the state of the art of CAD for accelerator chip design.

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