2020 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 2-5, 2020San Diego Mission Bay Resort

MP Associates, Inc.

THURSDAY November 07, 8:15am - 5:00pm | Westminster III

Workshop on Hardware and Algorithms for Learning On-a-Chip
Yiran Chen - Duke Univ.

Hsien-Hsin Lee - Facebook
Vikas Chandra - Facebook
Yu Wang - Tsinghua Univ.
Jae-Joon Kim -
Yingyan Lin - Rice Univ.
Tinoosh Mohsenin - Univ. of Maryland
Jaewoong Sim - Intel Corp.
Siddharth Garg - New York Univ.
Zhen Zhang - Univ. of California, Santa Barbara
Pierre-Emmanuel Gailiardon - Univ. of Utah
Catherine Schuman - Oak Ridge National Laboratory
Yiran Chen - Duke Univ.
Qinru Qiu - Syracuse Univ.
Yanzhi Wang - Northeastern Univ.
Jishen Zhao - Univ. of California, San Diego
In recent years, machine/deep learning algorithms has unprecedentedly improved the accuracies in practical recognition and classification tasks, some even surpassing human-level accuracy. However, to achieve incremental accuracy improvement, state-of-the-art deep neural network (DNN) algorithms tend to present very deep and large models, which poses significant challenges for hardware implementations in terms of computation, memory, and communication. This is especially true for edge devices and portable hardware applications, such as smartphones, machine translation devices, and smart wearable devices, where severe constraints exist in performance, power, and area. There is a timely need to map the latest complex learning algorithms to custom hardware, in order to achieve orders of magnitude improvement in performance, energy efficiency and compactness. Exemplary efforts from industry and academia include many application-specific hardware designs (e.g., xPU, FPGA, ASIC, etc.). Recent progress in computational neurosciences and nanoelectronic technology, such as emerging memory devices, will further help shed light on future hardware-software platforms for learning on-a-chip. The overarching goal of this workshop is to explore the potential of on-chip machine learning, to reveal emerging algorithms and design needs, and to promote novel applications for learning. It aims to establish a forum to discuss the current practices, as well as future research needs in the aforementioned fields.