2020 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 2-5, 2020San Diego Mission Bay Resort

MP Associates, Inc.

MONDAY November 04, 10:30am - 12:30pm | Westminster III
EVENT TYPE: SPECIAL SESSION

SESSION 1D
Design Automation and DNN for FPGAs
Organizers:
Wei Zhang - Hong Kong Univ. of Science and Technology
Yun Liang - Peking Univ., Beijing, China

Field-Programmable Gate Arrays (FPGAs) are increasingly used as hardware accelerators to implement various tasks due to their advantages of low power and massive parallelism. However, conventional manual implementation of RTL codes on FPGAs requires deep comprehension of the hardware architecture and great efforts. In order to lower the programming barrier and improve the design efficiency, it is crucial to develop the high-level design automation framework for the FPGA based design, such as high-level synthesis, automatic design optimization framework, etc. However, it also brings new challenges to the mapping flow and tool support for the FPGA implementation. At the same time, the machine learning workloads, especially the deep neural networks (DNNs) are increasingly deployed on FPGA for acceleration, where DNN’s deeper network and diverse branch structures pose great challenges for an efficient FPGA implementation.

This session presents six talks and addresses the above challenges from different perspectives. On one hand, it highlights new approaches for the automatic code generation, and synthesis flows for the efficient mapping of high-level designs on FPGA. On the other hand, it presents several DNN accelerator designs on FPGA with novel design optimization techniques.


1D.1 Zac : Towards Automatic Optimization and Deployment of Quantized Deep Neural Networks on Embedded Devices
 Speaker: Yun Liang - Peking Univ.
 Authors: Qingcheng Xiao - Peking Univ.
Yun Liang - Peking Univ.
1D.2Energy-Driven Dataflow Optimization for DNN on FPGA
 Speaker: Bei Yu - Chinese Univ. of Hong Kong
 Authors: Qi Sun - Chinese Univ. of Hong Kong
Tinghuan Chen - Chinese Univ. of Hong Kong
Jin Miao - Cadence Design System, Inc.
Bei Yu - Chinese Univ. of Hong Kong
1D.3Towards In-Circuit Tuning of Deep Learning Designs
 Speaker: Wayne Luk - Imperial College
 Authors: Zhiqiang Que - Imperial College
Daniel Holanda Noronha - Imperial College
Ruizhe Zhao - Imperial College
Steven J.E. Wilton - Imperial College
Wayne Luk - Imperial College
1D.4NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving
 Speaker: Cong Hao - Univ. of Illinois at Urbana-Champaign
 Authors: Cong Hao - Univ. of Illinois at Urbana-Champaign
Yao Chen - Advanced Digital Sciences Center
Deming Chen - Univ. of Illinois at Urbana-Champaign
Atif Sarwari - XMotors.ai
Daryl Sew - XMotors.ai
Ashutosh Dhar - Univ. of Illinois at Urbana-Champaign
Bryan Wu - XMotors.ai
Dongdong Fu - XMotors.ai
Jinjun Xiong - IBM Corp.
Wen-mei Hwu - Univ. of Illinois at Urbana-Champaign
Junli Gu - XMotors.ai
1D.5What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications
 Speaker: Olivier Sentieys - Univ. of Rennes 1
 Authors: Simon Rokicki - Univ Rennes, Inria
Joseph Paturel - Univ Rennes, Inria
Davide Pala - Univ. of Rennes 1
Olivier Sentieys - Univ. of Rennes 1
1D.6Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis
 Speaker: Wei Zhang - Hong Kong Univ. of Science and Technology, Hong Kong,
 Authors: Tingyuan Liang - Hong Kong Univ. of Science and Technology
Jieru Zhao - Hong Kong Univ. of Science and Technology
Liang Feng - Hong Kong Univ. of Science and Technology
Sharad Sinha - Indian Institute of Technology, Goa
Wei Zhang - Hong Kong Univ. of Science and Technology, Hong Kong,