2019 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 4-7, 2019The Westin Westminster Westminster, CO

MP Associates, Inc.
MONDAY November 04, 10:30am - 12:30pm | Westminster III
EVENT TYPE: SPECIAL SESSION
SESSION 1D
Design Automation and DNN for FPGAs
Organizer:
Yun Liang - Peking Univ., Beijing, China
With the rapidly increasing demands for computing capability, Field-Programmable Gate Arrays (FPGAs) are increasingly used as hardware accelerators to implement various tasks due to their advantages of low power and massive parallelism. However, conventional manual implementation of register transfer level (RTL) codes on FPGAs requires deep comprehension of the hardware architecture and great efforts, which can be error-prone as well. In order to lower the programming barrier and improve the design efficiency, it is crucial to develop the high-level design automation framework for the FPGA based design, such as high-level synthesis, automatic design optimization framework, etc. However, it also brings new challenges to the mapping flow and tool support for the FPGA implementation considering performance, power, and design verification. At the same time, the machine learning workloads, especially the deep neural networks (DNNs) are increasingly deployed on FPGA for acceleration for throughput improvement and power efficiency. Due to DNN’s deeper network and diverse branch structures, it poses great challenges for FPGA acceleration. For each type of layer, there exist many variants composed of distinct underlying operations while each operation has various implementations due to the data types that DNNs are quantized to. What makes it even more complicated is that the advances in FPGA technology enable various resources, including a high volume of DSPs, on-chip memory and off-chip bandwidth than previous generations. This session addresses the above challenges from different perspectives. On one hand, it highlights new approaches for the code automatic generation, and synthesis flows for the efficient mapping of high-level designs on FPGA. On the other hand, it presents several DNN accelerator designs on FPGA with novel design optimization techniques. There will be six talks in the session, trying to address the challenges of efficient design implementation on FPGA. The first four talks focused on the mapping flow of DNN acceleration in FPGA. The first talk explores quantization for DNNs on FPGAs and presents a framework to automatically optimize and deploy the quantized DNN models on FPGAs. The second talk optimizes the energy consumptions for DNN models under the constraints of FPGA board resources and latency requirements. The third talk presents a novel approach for supporting both synthesis and in-circuit debugging of deep learning designs. The fourth talk develops a hardware-oriented DNN/FPGA co-design strategy, to fully consider the properties of the target FPGA devices during the DNN model design, and FPGA resources and characteristics. The fifth talk considers the design of hardware processor core as well as its verification from a single high-level specification. The last talk presents Hi-ClockFlow, an automatic HLS platform, which can analyze the source code of a data flow application, explore the design space and optimize clock frequencies and HLS directives in the dataflow.

1D.1 Zac : Towards Automatic Optimization and Deployment of Quantized Deep Neural Networks on Embedded Devices
 Speaker: Yun Liang - Peking Univ.
 Authors: Qingcheng Xiao - Peking Univ.
Yun Liang - Peking Univ.
1D.2Energy-Driven Dataflow Optimization for DNN on FPGA
 Speaker: Bei Yu - Chinese Univ. of Hong Kong
 Authors: Qi Sun - Chinese Univ. of Hong Kong
Tinghuan Chen - Chinese Univ. of Hong Kong
Jin Miao - Cadence Design System, Inc.
Bei Yu - Chinese Univ. of Hong Kong
1D.3Towards In-Circuit Tuning of Deep Learning Designs
 Speaker: Wayne Luk - Imperial College
 Authors: Zhiqiang Que - Imperial College
Daniel Holanda Noronha - Imperial College
Ruizhe Zhao - Imperial College
Steven J.E. Wilton - Imperial College
Wayne Luk - Imperial College
1D.4NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving
 Speaker: Deming Chen - Univ. of Illinois at Urbana-Champaign
 Authors: Cong Hao - Univ. of Illinois at Urbana-Champaign
Yao Chen - Advanced Digital Sciences Center
Deming Chen - Univ. of Illinois at Urbana-Champaign
Atif Sarwari - XMotors.ai
Daryl Sew - XMotors.ai
Ashutosh Dhar - Univ. of Illinois at Urbana-Champaign
Bryan Wu - XMotors.ai
Dongdong Fu - XMotors.ai
Jinjun Xiong - IBM Corp.
Wen-mei Hwu - Univ. of Illinois at Urbana-Champaign
Junli Gu - XMotors.ai
1D.5What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications
 Speaker: Olivier Sentieys - Univ. of Rennes 1
 Authors: Simon Rokicki - Univ Rennes, Inria
Joseph Paturel - Univ Rennes, Inria
Davide Pala - Univ. of Rennes 1
Olivier Sentieys - Univ. of Rennes 1
1D.6Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis
 Speaker: Wei Zhang - Hong Kong Univ. of Science and Technology, Hong Kong,
 Authors: Tingyuan Liang - Hong Kong Univ. of Science and Technology
Jieru Zhao - Hong Kong Univ. of Science and Technology
Liang Feng - Hong Kong Univ. of Science and Technology
Sharad Sinha - Indian Institute of Technology, Goa
Wei Zhang - Hong Kong Univ. of Science and Technology, Hong Kong,