2019 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 4-7, 2019The Westin Westminster Westminster, CO

v class="event-details"> MP Associates, Inc.

TUESDAY November 06, 4:15pm - 6:15pm | Private Dining Room
EVENT TYPE: EMBEDDED TUTORIAL

SESSION 7E
The Need and Opportunities of Electromigration-Aware Integrated Circuit Design
Moderator:
Jens Lienig - Technische Univ. Dresden
Electromigration (EM) is becoming a progressively intractable design challenge due to increased interconnect current densities. It has changed from something designers “should” think about to something they “must” think about, i.e. become a requirement. The International Roadmap for Devices and Systems (IRDS) and the International Technology Roadmap for Semiconductors (ITRS) predict that semiconductor scale and interconnect cross-sections in semiconductor technologies will decrease further over the coming years. This continuing trend of IC down-scaling can easily lead to current densities that exceed their maximum allowable values. While analog designers have been aware of this problem for some time, increasingly digital designs are also affected. Accordingly, the ITRS indicates that all of today’s minimum-sized interconnects are EM-affected. The trend towards smaller line widths and smaller cross-sectional areas will continue at least until 2027, accompanied by an alarming increase in current densities in ICs going forward. As a consequence of these dramatic developments, any up-to date physical design methodology must be EM-aware; how to achieve this is the subject of this tutorial.
We first introduce the physical electromigration process and present its specific characteristics that can be affected during VLSI physical design. Examples of EM countermeasures that are applied in today’s commercial design flows are presented next. Here, we show how to improve the EM robustness of metallization patterns, we also consider mission profiles to obtain application-oriented current-density limits. The third presentation investigates the increasing interaction of EM with thermal migration. Finally, we conclude with a discussion of application examples to shift from a traditional (post-layout) EM verification towards a pro-active EM-aware physical design process. These methodologies, such as an EM-aware routing, increase EM-robustness of the layout with the overall goal of reducing the negative impact of EM on the circuit's reliability.

7E.1Motivation and Fundamentals of EM and its Mitigation in Today’s Design Flows
 Speaker: Jens Lienig - Technische Univ. Dresden
7E.2EM-Aware Layout Design and Mission Profiles in Industrial Practice
 Speakers: Juergen Scheible - Robert Bosch Center for Power Electronics
Goeran Jerke - Robert Bosch GmbH
7E.3Interaction of Thermal Effects, Thermal Migration and Electromigration
 Speaker: Roland Jancke - Fraunhofer Institute for Integrated Circuits
7E.4Methodologies for EM-Aware Design in Future Technology Nodes
 Speaker: Steve Bigalke - Technische Univ. Dresden
7E.5Paper Title: The Need and Opportunities of Electromigration-Aware Integrated Circuit Design
 Authors: Steve Bigalke - Technische Univ. Dresden
Jens Lienig - Technische Univ. Dresden
Goeran Jerke - Robert Bosch GmbH
Juergen Scheible - Robert Bosch Center for Power Electronics
Roland Jancke - Fraunhofer Institute for Integrated Circuits