2019 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 4-7, 2019The Westin Westminster Westminster, CO

v class="event-details"> MP Associates, Inc.

TUESDAY November 06, 10:30am - 12:00pm | Capri
EVENT TYPE: SPECIAL SESSION

SESSION 5D
Hardware Intellectual Property (IP) Protection Techniques: What, When, and How to Use?
Moderator:
Ozgur Sinanoglu - New York Univ., Abu Dhabi
Globalization of Integrated Circuit (IC) design is forcing the IC/ IP designers and users re-assess their trust in hardware. As the IC design flow spans the globe, driven by cost-conscious consumer electronics, hardware is increasingly prone to new kinds of attacks such as counterfeiting, hardware Trojans, side channel analysis, reverse engineering and IP piracy. An attacker, anywhere within this design flow, can reverse engineer the functionality of an IC/IP, steal and claim ownership of the IP, inject malicious circuitry (i.e., hardware Trojans) into the IC, or introduce counterfeits into the supply chain. Moreover, an untrusted IC fab may overbuild ICs and sell them illegally. The semiconductor industry is estimated to lose $4 billion annually due to these attacks. Many of these attacks hinge on the fact the attacker can obtain full control over the design. To thwart such adversaries, researchers have developed several techniques, namely IP metering, logic locking/encryption, camouflaging, and split manufacturing. These techniques are currently being used and/or considered for usage by companies. These techniques greatly differ in their threat models and security properties. Together, they address a wide spectrum of attackers—untrusted designer, untrusted foundry, untrusted testing facility, untrusted user, and a combination thereof. This tutorial brings in three experts on these topics to explain these techniques in a collective and cohesive way. The tutorial will explain what techniques to use against attackers, when to use them in the supply-chain, and how to use them in a provably-secure way. Techniques will be explained using concepts from IC design and test, graph theory, and cryptography. The presenters collectively have more than two decades of research experience in these topics, providing a wide coverage from theory to practice.

5D.1IP Protection in Untrusted Supply Chain
 Speaker: Farinaz Koushanfar - Univ. of California, San Diego
 Author: Farinaz Koushanfar - Univ. of California, San Diego
5D.2Customized Locking of IP Blocks on a Multi-Million-Gate SoC
 Speaker: Ozgur Sinanoglu - New York Univ., Abu Dhabi
 Authors: Ozgur Sinanoglu - New York Univ., Abu Dhabi
Abhrajit Sengupta - New York Univ.
Mohammed Nabeel - New York Univ., Abu Dhabi
Mohammed Ashraf - New York Univ., Abu Dhabi
5D.3Split Manufacturing
 Speaker: Jeyavijayan Rajendran - Texas A&M Univ.
 Author: Jeyavijayan Rajendran - Texas A&M Univ.