2019 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 4-7, 2019The Westin Westminster Westminster, CO

v class="event-details"> MP Associates, Inc.

MONDAY November 05, 1:45pm - 3:45pm | Riveria
EVENT TYPE: REGULAR SESSION

SESSION 2C
Architecting for Efficiency of Deep Learning
Moderator:
Meng Li - Facebook AI Silicon Research
The papers of this session aim to improve the efficiency of deep learning systems via optimizing the architecture for hardware, algorithm, and design methodology. The first two papers propose new hardware architecture for deep neural network accelerators. The third paper designs a new neural network architecture for energy-constrained applications. The fourth paper presents neural network-based design methodology for timing error prediction.

2C.1Tetris: Re-Architecting Convolutional Neural Network Computation for Machine Learning Accelerators
 Speaker: Hang Lu - Chinese Academy of Sciences
 Authors: Hang Lu - Chinese Academy of Sciences
Xin Wei - Chinese Academy of Sciences
Ning Lin - Chinese Academy of Sciences
Guihai Yan - Chinese Academy of Sciences
Xiaowei Li - Chinese Academy of Sciences
2C.2FCN-Engine: Accelerating Deconvolutional Layers in Classic CNN Processors
 Speaker: Kaijie Tu - Hefei Univ. of Technology
 Authors: Dawen Xu - Hefei Univ. of Technology
Kaijie Tu - Hefei Univ. of Technology
Ying Wang - Chinese Academy of Sciences
Cheng Liu - National Univ. of Singapore
Bingsheng He - National Univ. of Singapore
Huawei Li - Chinese Academy of Sciences
2C.3Designing Adaptive Neural Networks for Energy-Constrained Image Classification
 Speaker: Dimitrios Stamoulis - Carnegie Mellon Univ.
 Authors: Dimitrios Stamoulis - Carnegie Mellon Univ.
Ting-Wu (Rudy) Chin - Carnegie Mellon Univ.
Anand Krishnan Prakash - Carnegie Mellon Univ.
Haocheng Fang - Carnegie Mellon Univ.
Sribhuvan Sajja - Carnegie Mellon Univ.
Mitchell Bognar - Carnegie Mellon Univ.
Diana Marculescu - Carnegie Mellon Univ.
2C.4FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design
 Speaker: Jeff Zhang - New York Univ.
 Authors: Jeff Zhang - New York Univ.
Siddharth Garg - New York Univ.