2017 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 13-16, 2017Irvine Marriott Irvine, CA

MP Associates, Inc.
WEDNESDAY November 15, 10:15am - 12:15pm | SSR
EVENT TYPE: EMBEDDED TUTORIAL
SESSION 8D
Predictive Process Design Kit (PDK) to Accelerate Academic Research in VLSI Design and CAD
Organizer:
Saurabh Sinha - ARM Inc.
Academic research in VLSI design and CAD, especially for advanced technology nodes has been severely limited by the lack of quality process design kit (PDK). Most advanced technology circuit and CAD research employ either SPICE-only predictive technology models or scale 45nm OpenPDK libraries to sub-10 or 7nm node dimensions. These methods omit important effects such as layout-dependent middle-of-line (MOL) parasitics, BEOL parasitics, multiple patterning effects, etc. As a result, even though academics pursue relevant CAD and VLSI research topics, the results and observations are not always reliable. For CAD research, utilizing scaled GDS/LEF layout files from 45nm technology node to sub-14nm dimensions can lead to erroneous conclusions and the researchers might not be even targeting the relevant problems. To bridge this gap, the ASAP7 PDK targeting the 7nm process node was developed in 2016 as a joint collaboration between ARM and Arizona State University. This session will cover the latest development for the ASAP PDK, including ASAP5 targeting the 5nm technology node, standard cell library development using the ASAP7 PDK and a case study exploring 3D-IC research using the ASAP library. The primary goal of this session is to improve the awareness of the ICCAD audience regarding the potential of a ‘realistic’ process design kit for advanced circuit design and CAD research. The three papers will cover all aspects of the PDK, beginning from PDK development; technology assumptions and tool-flows to standard cell library development and design case-studies.

8D.1ASAP7 Predictive Design Kit Development And Cell Design Technology Co-Optimization
 Speaker: Vinay Vashishtha - Arizona State Univ.
 Authors: Vinay Vashishtha - Arizona State Univ.
Manoj Vangala - Arizona State Univ.
Lawrence Clark - Arizona State Univ.
8D.2Standard Cell Library Design and Optimization Methodology for ASAP7 PDK
 Speaker: Xiaoqing Xu - ARM Inc
 Authors: Xiaoqing Xu - ARM Inc
Nishi Shah - ARM Inc.
Andrew Evans - ARM Inc.
Saurabh Sinha - ARM Inc.
Brian Cline - ARM Inc.
Greg Yeric - ARM Inc.
8D.3Full-chip Monolithic 3D IC Design and Power Performance Analysis with ASAP7 Library
 Speaker: Kyungwook Chang - Georgia Institute of Technology
 Authors: Kyungwook Chang - Georgia Institute of Technology
Bon Woong Ku - Georgia Institute of Technology
Saurabh Sinha - ARM Inc.
Sung Kyu Lim - Georgia Institute of Technology