2019 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 4-7, 2019The Westin Westminster Westminster, CO

MP Associates, Inc.

TUESDAY November 14, 4:15pm - 6:15pm | Salons A & B1
EVENT TYPE: REGULAR SESSION

SESSION 7A
Taming Routability with Improved Placement
Moderator:
Stephen Yang - Xilinx Inc.
From ASICs to FPGAs, this session showcases the heterogeneous nature of placement to handle the critical issue of routing congestion. The first two papers perform macro-block placement to address routing challenges. The third paper proposes a new clustering approach for lithography hotspot pattern classification, and the final paper describes a clock-aware placement algorithm for large-scale heterogeneous FPGAs.

7A.1An Integrated-Spreading-Based Macro-Refining Algorithm for Large-Scale Mixed-Size Circuit Designs
 Speaker: Szu-To Chen - National Taiwan Univ.
 Authors: Szu-To Chen - National Taiwan Univ.
Yao-Wen Chang - National Taiwan Univ.
Tung-Chieh Chen - Maxeda Technology, Inc.
7A.2A Novel Damped-Wave Framework for Macro Placement
 Speaker: Chin-Hao Chang - National Taiwan Univ.
 Authors: Chin-Hao Chang - National Taiwan Univ.
Yao-Wen Chang - National Taiwan Univ.
Tung-Chieh Chen - Maxeda Technology, Inc.
7A.3GRASP based Metaheuristics for Layout Pattern Classification
 Speaker: Mingyu Woo - Ulsan National Institute of Science and Technology (UNIST)
 Authors: Mingyu Woo - Ulsan National Institute of Science and Technology (UNIST)
Seungwon Kim - Ulsan National Institute of Science and Technology (UNIST)
Seokhyeong Kang - Ulsan National Institute of Science and Technology (UNIST)
7A.4Clock-Aware Placement for Large-Scale Heterogeneous FPGAs
 Speaker: Yun-Chih Kuo - National Taiwan Univ.
 Authors: Yun-Chih Kuo - National Taiwan Univ.
Chau-Chin Huang - National Taiwan Univ.
Shih-Chun Chen - National Taiwan Univ.
Chun-Han Chiang - National Taiwan Univ.
Yao-Wen Chang - National Taiwan Univ.
Sy-Yen Kuo - National Taiwan Univ.