2017 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 13-16, 2017Irvine Marriott Irvine, CA

MP Associates, Inc.

WEDNESDAY November 04, 4:00pm - 6:00pm | Phoenix North

Make or Break - Synthesis, Simulation and Post-Silicon Validation
Miroslav Velev - Aries Design Automation, LLC
This session addresses correctness and verification at different levels of abstraction spanning synthesizing correct designs, transistor level simulation, and post-silicon validation. The first paper uses the popular IC3/PDR to synthesize reactive systems. The second paper proposes a new data structure for symbolic timing simulation at transistor level. The third paper introduces an approach for non-repeating stimuli for post silicon constrained random verification. The final paper considers post-silicon coverage monitoring.

9A.1Property-Directed Synthesis of Reactive Systems from Safety Specifications
 Speaker: Jie-Hong Roland Jiang - National Taiwan Univ.
 Authors: Ting-Wei Chiang - National Taiwan Univ.
Jie-Hong Roland Jiang - National Taiwan Univ.
9A.2Efficient Transistor-Level Symbolic Timing Simulation Using Cached Partial Circuit States
 Speaker: Clayton McDonald - Synopsys, Inc.
 Authors: Clayton McDonald - Synopsys, Inc.
Hsinwei Chou - Synopsys, Inc.
Vijay Durairaj - Synopsys, Inc.
Pey-Chang Kent Lin - Synopsys, Inc.
9A.3On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon Validation
 Speaker: Xiaobing Shi - McMaster Univ.
 Authors: Xiaobing Shi - McMaster Univ.
Nicola Nicolici - McMaster Univ.
9A.4Reducing Post-Silicon Coverage Monitoring Overhead with Emulation and Bayesian Feature Selection
 Speaker: Ricardo Ochoa Gallardo - Univ. of British Columbia
 Authors: Ricardo Ochoa Gallardo - Univ. of British Columbia
Alan J. Hu - Univ. of British Columbia
André Ivanov - Univ. of British Columbia
Maryam S. Mirian - Univ. of Tehran