MONDAY November 02, 1:30pm - 3:30pm | Phoenix North
EVENT TYPE: REGULAR SESSION
Flavio M. de Paula - IBM Corp.
In this session, the first three papers present advances in scheduling, acceleration, and architecture of high-level synthesis (HLS) systems. The session starts with an approach that exploits code transformation to improve HLS performance. The second paper uses an accelerator for parallelizing loops in hardware. The third contribution introduces a new "buslet" architecture to improve wire-ability of a HLS design. In the last paper, we take a new look at the state minimization problem for Mealy machines, using a Satisfiability formulation.
|2A.1||Code Transformations Based on Speculative SDC Scheduling|
|Speaker:||Marco Lattuada - Politecnico di Milano
|Authors:||Marco Lattuada - Politecnico di Milano
Fabrizio Ferrandi - Politecnico di Milano
|2A.2||ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests|
|Speaker:||Steve Dai - Cornell Univ.
|Authors:||Mingxing Tan - Cornell Univ.
Gai Liu - Cornell Univ.
Ritchie Zhao - Cornell Univ.
Steve Dai - Cornell Univ.
Zhiru Zhang - Cornell Univ.
|2A.3||Communication Scheduling and Buslet Synthesis for Low-Interconnect HLS Designs|
|Speaker:||Enzo Tartaglione - Univ. of Illinois at Chicago
|Authors:||Enzo Tartaglione - Univ. of Illinois at Chicago
Shantanu Dutt - Univ. of Illinois at Chicago
|2A.4||MeMin: SAT-based Exact Minimization of Incompletely Specified Mealy Machines|
|Speaker:||Andreas Abel - Saarland Univ.
|Authors:||Andreas Abel - Saarland Univ.
Jan Reineke - Saarland Univ.