2021 International Conference On
Computer-Aided Design

40th EDITION


The Premier Conference Devoted to Technical Innovations in
Electronic Design Automation
Virtual Technical Program:
November 1-4, 2021
Networking In-Person:
November 5, 2021





HOME » SUBMISSION » ACCEPTED SCIENTIFIC PAPERS

ACCEPTED SCIENTIFIC PAPERS


It is our pleasure to announce the accepted scientific papers of ICCAD 2021 that are as follows:


IDTitle
17OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler
19Automated Runtime-Aware Scheduling for Multi-Tenant DNN Inference on GPU
20Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noise
30Hybrid Analog-Digital In-Memory Computing
35MORE2: Morphable Encryption and Encoding for Secure NVM
39An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits
43Feedback-Guided Circuit Structure Mutation for Testing Hardware Model Checkers
51An Efficient Two-Phase Method for Prime Compilation of Non-Clausal Boolean Formulae
52Mobileware: A High-Performance MobileNet Accelerator with Channel Stationary Dataflow
55Overcoming the Memory Hierarchy Inefficiencies in Graph Processing Applications
59Traffic-Adaptive Power Reconfiguration for Energy-Efficient and Energy-Proportional Optical Interconnects
63Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis
67IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs
70From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning
75McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs
79dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference
82Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators, Part I: Determining Architectural State Variables
85BigIntegr: One-Pass Architectural Synthesis for Continuous-Flow Microfluidic Lab-on-a-Chip Systems
91DevelSet: Deep Neural Level Set for Instant Mask optimization
99TopoPart: a Multi-level Topology-Driven Partitioning Framework for Multi-FPGA Systems
101RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis
108Hyperdimensional Self-Learning Systems Robust to Technology Noise and Bit-Flip Attacks
112FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer
117AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA
120Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator
122SSR: A Skeleton-based Synthesis Flow for Hybrid Processing-in-RRAM Modes
126Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs
129Acceleration method for learning fine-layered optical neural networks
131An Optimal Algorithm for Splitter and Buffer Insertion in Adiabatic Quantum-Flux-Parametron Circuits
137DAPA: A Dataflow-aware Analytical Placement Algorithm for Modern Mixed-size Circuit Designs
145Lower Voltage for Higher Security: Using Voltage Overscaling to Secure Deep Neural Networks
152Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FPGAs
161Starfish: An Efficient P&R Co-Optimization Engine with A*-based Partial Rerouting
163UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction
169Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems
177GPU Overdrive Fault Attacks on Neural Networks
179A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU
184A Framework for Area-efficient Multi-task BERT Execution on ReRAM-based Accelerators
186A Convergence Monitoring Method for DNN Training of On-Device Task Adaptation
187A Unified Framework for Layout Pattern Analysis with Deep Causal Estimation
191Analytical Modeling of Transient Electromigration Stress based on Boundary Reflections
193CNN-Cap: Effective Convolutional Neural Network Based Capacitance Models for Full-Chip Parasitic Extraction
206G-CoS: GNN-Accelerator Co-Search Towards Both Better Accuracy and Efficiency
215Hotspot Detection via Multi-task Learning and Transformer Encoder
217Stealing Neural Network Models through the Scan Chain: A New Threat for ML Hardware
222Improving Inter-kernel Data Reuse With CTA-Page Coordination in GPGPU
229Relative-Scheduling-Based High-Level Synthesis for Flow-Based Microfluidic Biochips
232Manufacturing Cycle-Time Optimization Using Gaussian Drying Model for Inkjet-Printed Electronics
233A Row-Based Algorithm for Non-Integer Multiple-Cell-Height Placement
235Time-Division Multiplexing Based System-Level FPGA Routing
237Optical Routing Considering Waveguide Matching Constraints
244Enhanced Fast Boolean Matching based on Sensitivity Signatures Pruning
247ToPro: A Topology Projector and Waveguide Router for Wavelength-Routed Optical Networks-on-Chip
253Compatible Equivalence Checking of X-Valued Circuits
257HeteroCPPR: Accelerating Common Path Pessimism Removal with Heterogeneous CPU-GPU Parallelism
262Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs
268Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies
280Engineering an Efficient Boolean Functional Synthesis Engine
286pGRASS-Solver: A Parallel Iterative Solver for Scalable Power Grid Analysis Based on Graph Spectral Sparsification
292DARe: DropLayer-Aware Manycore ReRAM architecture for Training Graph Neural Networks
295From Specification to Topology: Automatic Power Converter Design via Reinforcement Learning
300Exploring eFPGA-based Redaction for IP Protection
313ScaleDNN: Data Movement Aware DNN Training on Multi-GPU
319An OCV-Aware Clock Tree Synthesis Methodology
321BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology
322Sampling-Based Approximate Logic Synthesis: An Explainable Machine Learning Approach
328Generalizable Cross-Graph Embedding for GNN-based Congestion Prediction
336BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework
338HyperSF: Spectral Hypergraph Coarsening via Flow-based Local Clustering
348ReIGNN: State Register Identification Using Graph Neural Networks for Circuit Reverse Engineering
351A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits
352GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs
362DeepFreeze: Cold Boot Attack and Model Recovery on Commercial EdgeML Device
363O-HAS: Optical Hardware Accelerator Search for Boosting Both Acceleration Performance and Development Speed
365Machine Learning-Based Test Pattern Generation for Neuromorphic Chips
366Crossbar based Processing in Memory Accelerator Architecture for Graph Convolutional Networks
368A Circuit-Based SAT Solver for Logic Synthesis
387CORLD: In-Stream Correlation Manipulation for Low-Discrepancy Stochastic Computing
391GAMER: GPU Accelerated Maze Routing
394Reliable Memristor-based Neuromorphic Design Using Variation- and Defect-Aware Training
398Automatic Routability Predictor Development Using Neural Architecture Search
410Aker: A Design and Verification Framework for Safe and Secure SoC Access Control
414Deferred Dropout: An Algorithm-Hardware Co-Design DNN Training Method Provisioning Consistent High Activation Sparsity
418AutoGTCO: Graph and Tensor Co-Optimize for Image Recognition with Transformers on GPU
423DALTA: A Decomposition-based Approximate Lookup Table Architecture
426When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning
431Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAs
439REREC: In-ReRAM Acceleration with Access-Aware Mapping for Personalized Recommendation
441Performance-Aware Common-centroid Placement and Routing of Transistor Arrays in Analog Circuits
447MinSC: An Exact Synthesis-Based Method for Minimal Area Stochastic Circuits under Relaxed Error Bound
468Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits
480Quarry: Quantization-based ADC Reduction for ReRAM-based Deep Neural Network Accelerators
481Graph Learning-Based Arithmetic Block Identification
486ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs
489Improving the Robustness of Redundant Execution with Register File Randomization
490Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization
499Positive/Negative Approximate Multipliers for DNN Accelerators
505Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State Compression
520Robust Time-Sensitive Networking with Delay Bound Analyses
523Accelerating Framework of Transformer by Hardware Design and Model Compression Co-Optimization
524iSTELLAR: intermittent Signature aTtenuation Embedded CRYPTO with Low-Level metAl Routing
538ReSpawn: Energy-Efficient Fault-Tolerance for Spiking Neural Networks considering Unreliable Memories
555Peripheral Circuitry Assisted Mapping Framework for Resistive Logic-In-Memory Computing
562Bounded Model Checking of Speculative Non-Interference
578LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs
579Massively Parallel Big Data Classification on a Programmable Processing In-Memory Architecture
581RNSiM: Efficient Deep Neural Network Accelerator Using Residue Number Systems
583AdaCon: Adaptive Context-Aware Object Detection for Resource-Constrained Embedded Devices
600HASHTAG: Hash Signatures for Online Detection of Fault-Injection Attacks on Deep Neural Networks
607AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow
612Circuit Deobfuscation from Power Side-Channels using Pseudo-Boolean SAT
625Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation
627Manatee: A Fast LLVM-Based RISC-V Binary Translator
630GPU-accelerated Critical Path Generation with Path Constraints
654Optimal Mapping for Near-Term Quantum Architectures based on Rydberg Atoms
670LayerPipe: Accelerating Deep Neural Network Training by Intra-Layer and Inter-Layer Gradient Pipelining and Multiprocessor Scheduling
674Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning
677Theoretical Analysis and Evaluation of NoCs with Weighted Round Robin Arbitration
681Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNs
713Split Compilation for Security of Quantum Circuits
714Heuristics for Million-scale Two-level Logic Minimization
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