2021 International Conference On
Computer-Aided Design

40th EDITION


The Premier Conference Devoted to Technical Innovations in
Electronic Design Automation
Virtual Technical Program:
November 1-4, 2021
Networking In-Person:
November 5, 2021





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SESSION
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KEYNOTE
1 2 3 4


SPONSOR'S SESSION
1 2

MONDAY, NOV 01, 2021

7:20 - 8:00 am Opening Session and Awards

KEYNOTE 1
8:00 - 9:00 am KEYNOTE 1
Moderator: Tulika Mitra, National University of Singapore
  • Efficient Computing for AI and Robotics: From Hardware Accelerators to Algorithm Design
    Vivienne Sze, Massachusetts Institute of Technology (MIT)
SESSION 1
9:00 - 9:45 am SESSION 1A | Efficient DNN Training and Secure/Robust DNN Inference
Moderator: Yingyan Lin, Rice University
  • Lower Voltage for Higher Security: Using Voltage Overscaling to Secure Deep Neural Networks
    Md Shohidul Islam, George Mason University, Ihsen Alouani, IEMN lab, INSA Hauts-de-France, Université Polytechnique Hauts-De-France, Khaled N. Khasawneh, George Mason University
  • Deferred Dropout: An Algorithm-Hardware Co-Design DNN Training Method Provisioning Consistent High Activation Sparsity
    Kangkyu Park, Korea Advanced Institute of Science and Technology, Yunki Han, Korea Advanced Institute of Science and Technology, Lee-Sup Kim, Korea Advanced Institute of Science and Technology
  • LayerPipe: Accelerating Deep Neural Network Training by Intra-Layer and Inter-Layer Gradient Pipelining and Multiprocessor Scheduling
    Nanda Unnikrishnan, University of Minnesota, Keshab Parhi, University of Minnesota
  • Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noise
    Xiaoxuan Yang, Duke University, Syrine Belakaria, Washington State University, Biresh Kumar Joardar, Duke University, Huanrui Yang, Duke University, Jana Doppa, Washington State University, Partha Pratim Pande, Washington State University, Krishnendu Chakrabarty, Duke University, Hai (Helen) Li, Duke University
9:00 - 9:45 am SESSION 1B | Advances in Boolean Methods for Synthesis
Moderator: Cheng Tan, Pacific Northwest National Laboratory
  • Engineering an Efficient Boolean Functional Synthesis Engine
    Priyanka Golia, Indian Institute of Technology Kanpur, National University of Singapore, Friedrich Slivovsky, TU Wien, Subhajit Roy, Indian Institute of Technology Kanpur, Kuldeep S. Meel, National University of Singapore
  • Enhanced Fast Boolean Matching based on Sensitivity Signatures Pruning
    Jiaxi Zhang, Peking University, Liwei Ni, Pengcheng Laboratory, Shenggen Zheng, Pengcheng Laboratory, Hao Liu, Peking University, Xiangfu Zou, Pengcheng Laboratory, Feng Wang, Peking University, Guojie Luo, Peking University
  • An Efficient Two-Phase Method for Prime Compilation of Non-Clausal Boolean Formulae
    Weilin Luo, Sun Yat-sen University, Hai Wan, Sun Yat-sen University, Hongzhen Zhong, Sun Yat-sen University, Ou Wei, University of Toronto, Biqing Fang, Sun Yat-sen University, Xiaotong Song, Sun Yat-sen University
  • Heuristics for Million-scale Two-level Logic Minimization
    Mahdi Nazemi, University of Southern California, Hitarth Kanakia, University of Southern California, Massoud Pedram, University of Southern California
9:00 - 9:45 am SESSION 1C | Power Model Calibration and Computing with Approximation and Uncertainty
Moderator: Seda Ogrenci-Memik, Northwestern University
  • McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs
    Jianwang Zhai, Tsinghua University, Chen Bai, The Chinese University of Hong Kong, Binwu Zhu, The Chinese University of Hong Kong, Yici Cai, Tsinghua University, Qiang Zhou, Tsinghua University, Bei Yu, The Chinese University of Hong Kong
  • Positive/Negative Approximate Multipliers for DNN Accelerators
    Ourania Spantidi, Southern Illinois University Carbondale, Georgios Zervakis, Karlsruher Institut für Technologie, Iraklis Anagnostopoulos, Southern Illinois University Carbondale, Hussam Amrouch, University of Stuttgart, Joerg Henkel, KIT
  • MinSC: An Exact Synthesis-Based Method for Minimal Area Stochastic Circuits under Relaxed Error Bound
    Xuan Wang, Shanghai Jiao Tong University, Zhufei Chu, Ningbo University, Zhufei Chu, Ningbo University, Weikang Qian, Shanghai Jiao Tong University
  • CORLD: In-Stream Correlation Manipulation for Low-Discrepancy Stochastic Computing
    Sina Asadi, University of Louisiana at Lafayette, M. Hassan Najafi, University of Louisiana at Lafayette, Mohsen Imani, UC Irvine
9:00 - 9:45 am SPECIAL SESSION 1D | Cross Layer Design Solutions for Energy-Efficient and Secure Edge AI
Moderator: Muhammad Shafique, New York University Abu Dhabi
  • TinyML: Massive Opportunity for Edge AI when Machine Intelligence meets the Real World of Billions of Sensors
    Evgeni Gousev, Qualcomm Technologies, Inc.
  • Challenges and Opportunities in Security and Reliability of Edge AI
    Aviv Barkai, Intel
  • A Hardware and Software Co-Design Framework for Energy-Efficient Edge AI
    Nitthilan Kannappan Jayakodi, Washington State University, Janardhan Rao Doppa, Washington State University, Partha Pratim Pande, Washington State University
  • Energy-Efficient and Secure Edge AI
    Muhammad Shafique, New York University Abu Dhabi, Alberto Marchisio, TU Wien, Rachmad Vidya Wicaksana Putra, TU Wien, Muhammad Abdullah Hanif, TU Wien

SESSION 2
9:45 - 10:30 am SESSION 2A | Efficient DNN Inference and Tools
Moderator: Ziyun Li, Facebook
  • Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator
    Fangxin Liu, Shanghai Jiao Tong University, Wenbo Zhao, Shanghai Jiao Tong University, Zhezhi He, Shanghai Jiao Tong University, Zongwu Wang, Shanghai Jiao Tong University, Yilong Zhao, Shanghai Jiao Tong University, Yongbiao Chen, Shanghai Jiao Tong University, Li Jiang, Shanghai Jiao Tong University
  • Crossbar based Processing in Memory Accelerator Architecture for Graph Convolutional Networks
    Nagadastagiri Challapalle, The Pennsylvania State University, Karthik Swaminathan, IBM T.J Watson Research Center, Nandhini Chandramoorthy, IBM Research, Vijaykrishnan Narayanan, Penn State University
  • Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNs
    Elbruz Ozen, University of California San Diego, Alex Orailoglu, University of California San Diego
  • Generalizable Cross-Graph Embedding for GNN-based Congestion Prediction
    Amur Ghose, Huawei, Vincent Zhang, Huawei, Yingxue Zhang, Huawei Noah's Ark Lab, Huawei Technologies Canada, Dong Li, Huawei, Wulong Liu, Huawei Noah's Ark Lab, Mark Coates, McGill University
9:45 - 10:30 am SESSION 2B | LOLOL: Lots of Logic Locking and Unlocking
Moderator: Sri Parameswaran, The University of New South Wales
  • UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction
    Lilas Alrahis, New York University Abu Dhabi, Satwik Patnaik, Texas A&M University, Muhammad Hanif, Vienna University of Technology, Muhammad Shafique, New York University Abu Dhabi, Ozgur Sinanoglu, New York University Abu Dhabi
  • Circuit Deobfuscation from Power Side-Channels using Pseudo-Boolean SAT
    Kaveh Shamsi, University of Texas at Dallas, Yier Jin, University of Florida
  • Exploring eFPGA-based Redaction for IP Protection
    Jitendra Bhandari, New York University, Abdul Khader Thalakkattu Moosa, New York University, Benjamin Tan, University of Calgary, Christian Pilato, Politecnico di Milano, Ganesh Gore, University of Utah, Xifan Tang, University of Utah, Scott Temple, University of Utah, Pierre-Emmanuel Gaillardon, University of Utah, Ramesh Karri, New York University
  • LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs
    Hassan Nassar, Karlsruher Institut für Technologie, Hanna Al Zughbi, Independent, Dennis Gnad, Karlsruher Institut für Technologie, Lars Bauer, Karlsruher Institut für Technologie, Mehdi Tahoori, Karlsruher Institut für Technologie, Jörg Henkel, Karlsruher Institut für Technologie
9:45 - 10:30 am SESSION 2C | Quantum CAD Matters
Moderator: Anupam Chattopadhyay, Nanyang Technological University
  • Optimal Mapping for Near-Term Quantum Architectures based on Rydberg Atoms
    Sebastian Brandhofer, University of Stuttgart, Hans Peter Büchler, University of Stuttgart, Ilia Polian, University of Stuttgart
  • An Optimal Algorithm for Splitter and Buffer Insertion in Adiabatic Quantum-Flux-Parametron Circuits
    Chao-Yuan Huang, National Tsing Hua University, Yi-Chen Chang, National Tsing Hua University, Ming-Jer Tsai, National Tsing Hua University, Tsung-Yi Ho, National Tsing Hua University
  • A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits
    Ching-Cheng Wang, National Tsing Hua University, Wai-Kei Mak, National Tsing Hua University
  • Split Compilation for Security of Quantum Circuits
    Abdullah Ash- Saki, Pennsylvania State University, Aakarshitha Suresh, Pennsylvania State University, Rasit Onur Topaloglu, IBM, Swaroop Ghosh, Pennsylvania State University
9:45 - 10:30 am SESSION 2D | Multi-Core System Design and Optimization for the Big Data Era
Moderator: Katzalin Olcoz Herrero, Complutense University of Madrid
  • BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework
    Chen Bai, The Chinese University of Hong Kong, Qi Sun, The Chinese University of Hong Kong, Jianwang Zhai, Tsinghua University, Yuzhe Ma, The Chinese University of Hong Kong, Bei Yu, The Chinese University of Hong Kong, Martin Wong, The Chinese University of Hong Kong
  • DARe: DropLayer-Aware Manycore ReRAM architecture for Training Graph Neural Networks
    Aqeeb Iqbal Arka, Washington State University, Biresh Kumar Joardar, Duke University, Jana Doppa, Washington State University, Partha Pratim Pande, Washington State University, Krishnendu Chakrabarty, Duke University
  • IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs
    Nathaniel Pinckney, NVIDIA Corporation, Rangharajan Venkatesan, NVIDIA Corporation, Ben Keller, NVIDIA Corporation, Brucek Khailany, NVIDIA Corporation
  • Theoretical Analysis and Evaluation of NoCs with Weighted Round Robin Arbitration
    Sumit Mandal, University of Wisconsin-Madison, Jie Tong, University of Wisconsin-Madison, Raid Ayoub, Intel Corporation, Michael Kishinevsky, Intel Corporation, Ahmed Abousamra, Intel Corporation, Umit Ogras, University of Wisconsin-Madison
SESSION 3
10:30 - 11:00 am SESSION 3A | Algorithm-Hardware Co-Design for Machine Learning Hardware Accelerators
Moderator: Nagarajan Kandasamy, Drexel University
  • Reliable Memristor-based Neuromorphic Design Using Variation- and Defect-Aware Training
    Di Gao, Zhejiang University, Grace Li Zhang, Technical University of Munich, Xunzhao Yin, Zhejiang University, Bing Li, Technical University of Munich, Ulf Schlichtmann, Technical University of Munich, Cheng Zhuo, Zhejiang University
  • REREC: In-ReRAM Acceleration with Access-Aware Mapping for Personalized Recommendation
    Yitu Wang, Duke University, Zhenhua Zhu, Tsinghua University, Fan Chen, Indiana University, Mingyuan Ma, Duke University, Guohao Dai, Tsinghua University, Yu Wang, Tsinghua University, Hai (Helen) Li, Duke University, Yiran Chen, Duke University
  • RNSiM: Efficient Deep Neural Network Accelerator Using Residue Number Systems
    Arman Roohi, University of Nebraska-Lincoln, Mohammad Reza Taheri, Independent Researcher, Shaahin Angizi, New Jersey Institute of Technology, Deliang Fan, Arizona State University
10:30 - 11:00 am SESSION 3B | Routing with Wires and Light
Moderator: Mehmet Yildiz, Cadence Design Systems
  • Time-Division Multiplexing Based System-Level FPGA Routing
    Wei-Kai Liu, National Taiwan University Ming-Hung Chen, National Taiwan University, Chia-Ming Chang, National Taiwan University, Chen-Chia Chang, National Taiwan University, Yao-Wen Chang, National Taiwan University
  • Optical Routing Considering Waveguide Matching Constraints
    Fu-Yu Chuang, National Taiwan University, Yao-Wen Chang, National Taiwan University
  • GAMER: GPU Accelerated Maze Routing
    Shiju Lin, The Chinese University of Hong Kong, Jinwei Liu, The Chinese University of Hong Kong, Martin Wong, The Chinese University of Hong Kong
10:30 - 11:00 am SESSION 3C | CAD for Novel Electronic Applications
Moderator: Shaloo Rakheja, University of Illinois at Urbana-Champaign
  • Manufacturing Cycle-Time Optimization Using Gaussian Drying Model for Inkjet-Printed Electronics
    Tsun-Ming Tseng, Technical University of Munich, Meng Lian, Technical University of Munich, Mengchu Li, Technical University of Munich, Philipp Rinklin, Technical University of Munich, Leroy Grob, Technical University of Munich, Bernhard Wolfrum, Technical University of Munich, Ulf Schlichtmann, Technical University of Munich
  • ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs
    Sanmitra Banerjee, Duke University, Arjun Chaudhuri, Duke University, Jinwoo Kim, Georgia Institute of Technology, Gauthaman Murali, Georgia Institute of Technology, Mark Nelson, SkyWater Technology, Sung Kyu Lim, Georgia Tech, Krishnendu Chakrabarty, Duke University
  • Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation
    Imam Al Razi, University of Arkansas, Quang Le, University of Arkansas, H. Alan Mantooth, University of Arkansas, Yarui Peng, University of Arkansas
10:30 - 11:00 am SPECIAL SESSION 3D | Quantum Machine Learning: From Algorithm to Applications
Moderator: Anupam Chattopadhyay, Nanyang Technological University
  • Quantum Machine Learning for Quantum Applications
    Xiaodi Wu, University of Maryland
  • Mode connectivity in the QCBM loss landscape
    Kathleen Hamilton, Oak Ridge National Lab
  • Application of Quantum Machine Learning in Finance
    Marco Pistoia, JPMorgan Chase
  • Quantum-Classical Hybrid Machine Learning Architectures for Image Classification
    Mahabubul Alam, Pennsylvania State University, Satwik Kundu, Pennsylvania State University, Rasit Topaloglu, IBM, Swaroop Ghosh, Pennsylvania State University
11:00 am - 01:00 pm ACM Student Research Competition at ICCAD 2021
Organizers: Meng Li, Facebook, Cong Hao, Georgia Institute of Technology



Note Agenda time zone is UTC-7 / PDT (CALIFORNIA)
Start - end: 7:20 AM - 12:00 PM PDT (CALIFORNIA), 03:20 - 08:00 PM CET (GERMANY), 10:20 PM - 03:00 AM CST (CHINA)

TO THE TOP

TUESDAY, NOV 02, 2021


SESSION 4
7:20 - 8:00 am SESSION 4A | Acceleration of Emerging Deep Learning Techniques
Moderator: Janardhan Rao Doppa, Washington State University
  • O-HAS: Optical Hardware Accelerator Search for Boosting Both Acceleration Performance and Development Speed
    Mengquan Li, Rice University, Zhongzhi Yu, Rice University, Yongan Zhang, Rice University, Yonggan Fu, Rice University, Yingyan Lin, Rice University
  • Acceleration method for learning fine-layered optical neural networks
    Kazuo Aoyama, NTT Communication Science Laboratories, Hiroshi Sawada, NTT Communication Science Laboratories
  • Mobileware: A High-Performance MobileNet Accelerator with Channel Stationary Dataflow
    Sungju Ryu, Pohang University of Science and Technology, Youngtaek Oh, Pohang University of Science and Technology, Jae-Joon Kim, Postech
  • A Framework for Area-efficient Multi-task BERT Execution on ReRAM-based Accelerators
    Myeonggu Kang, Korea Advanced Institute of Science and Technology, Hyein Shin, Korea Advanced Institute of Science and Technology, Jaekang Shin, Korea Advanced Institute of Science and Technology, Lee-Sup Kim, Korea Advanced Institute of Science and Technology
7:20 - 8:00 am SESSION 4B | Resilient and Efficient Embedded Applications
Moderator: Leonidas Kosmidis, Barcelona Supercomputing Center
  • Robust Time-Sensitive Networking with Delay Bound Analyses
    Guoqi Xie, Hunan University, Xiangzhen Xiao, Hunan University, Hong Liu, Shanghai Trusted Industrial Control Platform Co., Ltd., Li Renfa, Hunan University, Wanli Chang, University of York
  • HASHTAG: Hash Signatures for Online Detection of Fault-Injection Attacks on Deep Neural Networks
    Mojan Javaheripi, University of California San Diego, Farinaz Koushanfar, University of California San Diego
  • A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU
    Wenqian Zhao, The Chinese University of Hong Kong, Qi Sun, The Chinese University of Hong Kong, Yang BAI, The Chinese University of Hong Kong, Haisheng Zheng, SmartMore, Wenbo Li, The Chinese University of Hong Kong, Bei Yu, The Chinese University of Hong Kong, Martin Wong, The Chinese University of Hong Kong
  • AdaCon: Adaptive Context-Aware Object Detection for Resource-Constrained Embedded Devices
    Marina Neseem, Brown University, Sherief Reda, Brown University
7:20 - 8:00 am SESSION 4C | Resilient and Efficient Embedded Applications
Moderator: Abhijit Chatterjee, Georgia Tech
  • Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State Compression
    Cheng Zeng, Fudan University, Fan Yang, Fudan University, Xuan Zeng, Fudan University
  • Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators, Part I: Determining Architectural State Variables
    Yu Zeng, Princeton University, Bo-Yuan Huang, Princeton University, Hongce Zhang, Princeton University, Aarti Gupta, Princeton University, Sharad Malik, Princeton University
  • Machine Learning-Based Test Pattern Generation for Neuromorphic Chips
    Hsiao-Yin Tseng, Graduate Institute of Electronics Engineering, National Taiwan University, I-Wei Chiu, Graduate Institute of Electronics Engineering, National Taiwan University, Mu-Ting Wu, Graduate Institute of Electronics Engineering, National Taiwan University, Chien-Mo Li, Graduate Institute of Electronics Engineering, National Taiwan University
  • Manatee: A Fast LLVM-Based RISC-V Binary Translator
    Samuel Riedel, ETH Zürich, Fabian Schuiki, ETH Zürich, Paul Scheffler, Integrated Systems Laboratory, ETH Zürich, Florian Zaruba, ETH Zürich, Luca Benini, Università di Bologna, and ETH Zürich
7:20 - 8:00 am SPECIAL SESSION 4D | VLSI for 5G and Beyond Wireless in the AI Era: Algorithm, Hardware and System
Moderator: Jiang Hu, Texas A&M University
  • FedSwap: A Federated Learning based 5G Decentralized Dynamic Spectrum Access System
    Zhihui Gao, Duke University, Ang Li, Duke University, Yunfan Gao, ETH Zürich, Bing Li, Capital Normal University, Yu Wang, Tsinghua University, Yiran Chen, Duke University
  • A Hybrid FPGA-ASIC Delayed Feedback Reservoir System to Enable Spectrum Sensing/Sharing for Low Power IoT Devices
    Osaze Shears, Virginia Polytechnic Institute and State University, Kangjun Bai, Virginia Polytechnic Institute and State University, Lingjia Liu, Virginia Polytechnic Institute and State University, Yang Cindy Yi, Virginia Polytechnic Institute and State University
  • Algorithm and Hardware Co-design for Deep Learning-powered Channel Decoder: A Case Study
    Boyang Zhang, Rutgers University, Yang Sui, Rutgers University, Lingyi Huang, Rutgers University, Siyu Liao, Amazon, Chunhua Deng, ScaleFlux, Bo Yuan, Rutgers University
  • 5G and Beyond Wireless in AI Era: ML-Driven Performance-Adaptive Terahertz Transceivers
    Payam Heydari, University of California, Irvine

KEYNOTE 2
8:00 - 9:00 am KEYNOTE 2
Moderator: Tsung-Yi Ho, National Tsing Hua University
  • Challenges and opportunities in GaN power electronics
    Elison Matioli, Ecole Polytechnique Fédérale de Lausanne (EPFL)

SESSION 5
9:00 - 9:45 am SESSION 5A | Hardware Software Co-Design for Advanced Deep Neural Networks
Moderator: Lilas M. Alrahis, New York University Abu Dhabi
  • A Convergence Monitoring Method for DNN Training of On-Device Task Adaptation
    Seungkyu Choi, Korea Advanced Institute of Science and Technology, Jaekang Shin, Korea Advanced Institute of Science and Technology, Lee-Sup Kim, Korea Advanced Institute of Science and Technology
  • Automated RunTime-Aware Scheduling for Multi-Tenant DNN Inference on GPU
    Fuxun Yu, George Mason University, Shawn Bray, University of Maryland, Baltimore County, Di Wang, Microsoft, Longfei Shangguan, Microsoft, Xulong Tang, University of Pittsburgh, Chenchen Liu, University of Maryland, Baltimore County, Xiang Chen, George Mason University
  • AutoGTCO: Graph and Tensor Co-Optimize for Image Recognition with Transformers on GPU
    Yang Bai, The Chinese University of Hong Kong, Xufeng Yao, The Chinese University of Hong Kong, Qi Sun, The Chinese University of Hong Kong, Bei Yu, The Chinese University of Hong Kong
  • G-CoS: GNN-Accelerator Co-Search Towards Both Better Accuracy and Efficiency
    Yongan Zhang, Rice University, Haoran You, Rice University, Yonggan Fu, Rice University, Tong Geng, Pacific Northwest National Laboratory, Ang Li, Pacific Northwest National Laboratory, Yingyan Lin, Rice University
9:00 - 9:45 am SESSION 5B | Security of ML Systems
Moderator: Benjamin Tan, University of Calgary
  • Hyperdimensional Self-Learning Systems Robust to Technology Noise and Bit-Flip Attacks
    Prathyush Poduval, University of California, Irvine, Yang Ni, University of California, Irvine, Kai Ni, Rochester Institute of Technology, Yeseong Kim, Daegu Gyeongbuk Institute of Science and Technology, Raghavan Kumar, Intel Labs, Rosario Cammarota, Intel Labs, Mohsen Imani, University of California, Irvine
  • GPU Overdrive Fault Attacks on Neural Networks
    Majid Sabbagh, Northeastern University, Yunsi Fei, Northeastern University, David Kaeli, Northeastern University
  • Stealing Neural Network Models through the Scan Chain: A New Threat for ML Hardware
    Seetal Potluri, North Carolina State University, Aydin Aysu, North Carolina State University
  • DeepFreeze: Cold Boot Attack and Model Recovery on Commercial EdgeML Device
    Yoo-Seung Won, Temasek Laboratories, Nanyang Technological University, Soham Chatterjee, Nanyang Technological University, Dirmanto Jap, Temasek Laboratories, Nanyang Technological University, Shivam Bhasin, Temasek Laboratories, Nanyang Technological University, Arindam Basu, Nanyang Technological University
9:00 - 9:45 am SESSION 5C | Managing Complexity with Cell Design and Partitioning
Moderator: Patrick H. Madden, SUNY Binghamton University
  • Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis
    Kyeonghyeon Baek, Seoul National University, Taewhan Kim, Seoul National University
  • Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies
    Andreas Krinke, Technische Universität Dresden, Shubham Rai, Technische Universität Dresden, Akash Kumar, Technische Universität Dresden, Jens Lienig, Technische Universität Dresden
  • HyperSF: Spectral Hypergraph Coarsening via Flow-based Local Clustering
    Ali Aghdaei, Stevens Institute of Technology, Zhiqiang Zhao, Stevens Institute of Technology, Zhuo Feng, Stevens Institute of Technology
  • TopoPart: a Multi-level Topology-Driven Partitioning Framework for Multi-FPGA Systems
    Dan Zheng, The Chinese University of Hong Kong, Xinshi Zang, The Chinese University of Hong Kong, Martin Wong, The Chinese University of Hong Kong
9:00 - 9:45 am SESSION 5D | TUTORIAL: Hardware Aware Learning for Medicine
Moderator: Zhezhi He, Shanghai Jiaotong University
  • Contrastive Learning with Temporal Correlated Medical Iges: A Case Study ing Lung Segmentation in Chest X-Rays
    Dewen Zeng, University of Notre Dame, John N Kheir, Boston Children's Hospital/Harvard Medical School, Peng Zeng, Boston Children's Hospital, Yiyu Shi, University of Notre Dame
  • Federated Contrastive Learning for Dermatological Disease Diagnosis via On-device Learning
    Yawen Wu, University of Pittsburgh, Dewen Zeng, University of Notre Dame, Zhepang Wang, George Mason University, Yi Sheng, George Mason University, Lei Yang, University of New Mexico, Alaina J James, University of Pittsburgh Medical Center, Yiyu Shi, University of Notre Dame, Jingtong Hu, University of Pittsburgh
  • Optimizing FPGA-based Accelerator Design for Large-Scale Molecular Similarity Search
    Hongwu Peng, University of Connecticut, Shiyang Chen, Stevens Institute of Technology, Zhepeng Wang, George Mason University, Junhuan Yang, University of New Mexico, Scott Weitze, Stevens Institute of Technology, Tong Geng, Pacific Northwest National Laboratory, Ang Li, Pacific Northwest National Laboratory, Jinbo Bi, University of Connecticut, Minghu Song, University of Connecticut, Weiwen Jiang, George Mason University, Hang Liu, Stevens Institute of Technology, Caiwen Ding, University of Connecticut
  • FL-DISCO: Federated Generative Adversarial Network for Graph-based Molecule Drug Discovery
    Daniel Manu, University of New Mexico, Yi Sheng, George Mason University, Junhuan Yang, University of New Mexico, Jieren Deng, University of Connecticut, Tong Geng, Pacific Northwest National Laboratory, Ang Li, Pacific Northwest National Laboratory, Caiwen Ding, University of Connecticut, Weiwen Jiang, George Mason University, Lei Yang, University of New Mexico

SESSION 6
9:45 - 10:30 am SESSION 6A | Brain-Inspired Computing and Microfluidic Bio-chips
Moderator: Mohamed Ibrahim, University of California, Berkeley
  • ReSpawn: Energy-Efficient Fault-Tolerance for Spiking Neural Networks considering Unreliable Memories
    Rachmad Vidya Wicaksana Putra, Vienna University of Technology, Muhammad Abdullah Hanif, Vienna University of Technology, Muhammad Shafique, New York University Abu Dhabi
  • Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization
    Ming-Liang Wei, National Taiwan University, Mikail Yayla, TU Dortmund, Shu-Yin Ho, Macronix, Jian-Jia Chen, TU Dortmund, Chia-Lin Yang, National Taiwan University, Hussam Amrouch, University of Stuttgart
  • BigIntegr: One-Pass Architectural Synthesis for Continuous-Flow Microfluidic Lab-on-a-Chip Systems
    Xing Huang, Technical University of Munich, Youlin Pan, Fuzhou University, Zhen Chen, Fuzhou University, Wenzhong Guo, Fuzhou University, Robert Wille, Johannes Kepler University Linz, Tsung-Yi Ho, National Tsing Hua University, Ulf Schlichtmann, Technical University of Munich
  • Relative-Scheduling-Based High-Level Synthesis for Flow-Based Microfluidic Biochips
    Fangda Zuo, Technical University of Munich, Mengchu Li, Technical University of Munich, Tsun-Ming Tseng, Technical University of Munich, Tsung-Yi Ho, National Tsing Hua University, Ulf Schlichtmann, Technical University of Munich
9:45 - 10:30 am SESSION 6B | New Techniques in Timing and Power Analysis
Moderator: Siddhartha Nath, NVIDIA
  • BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology
    Vidya A. Chhabria, University of Minnesota, Kishor Kunal, University of Minnesota, Masoud Zabihi, University of Minnesota, Sachin S. Sapatnekar, University of Minnesota
  • FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer
    Rongjian Liang, Texas A&M University, Jinwook Jung, IBM Research, Hua Xiang, IBM Research, Lakshmi Reddy, IBM Research, Alexey Lvov, IBM Corp., Jiang Hu, Texas A&M University, Gi-Joon Nam, IBM Research
  • HeteroCPPR: Accelerating Common Path Pessimism Removal with Heterogeneous CPU-GPU Parallelism
    Zizheng Guo, Peking University, Tsung-Wei Huang, University of Utah, Yibo Lin, Peking University
  • GPU-accelerated Critical Path Generation with Path Constraints
    Guannan Guo, University of Illinois, Tsung-Wei Huang, University of Utah, Yibo Lin, Peking University, Martin Wong, The Chinese University of Hong Kong
9:45 - 10:30 am SESSION 6C | Machine Learning Methods for DFM
Moderator: Jhih-Rong Gao, Flex Logix
  • DevelSet: Deep Neural Level Set for Instant Mask optimization
    Guojin Chen, The Chinese University of Hong Kong, Ziyang Yu, The Chinese University of Hong Kong, Hongduo Liu, The Chinese University of Hong Kong, Yuzhe Ma, The Chinese University of Hong Kong, Bei Yu, The Chinese University of Hong Kong
  • Hotspot Detection via Multi-task Learning and Transformer Encoder
    Binwu Zhu, The Chinese University of Hong Kong, Ran Chen, The Chinese University of Hong Kong, Xinyun Zhang, SmartMore, Fan Yang, Fudan University, Xuan Zeng, Fudan University, Bei Yu, The Chinese University of Hong Kong, Martin Wong, The Chinese University of Hong Kong
  • A Unified Framework for Layout Pattern Analysis with Deep Causal Estimation
    Ran Chen, The Chinese University of Hong Kong, Shoubo Hu, Huawei Noah's Ark Lab, Zhitang Chen, Huawei Noah's Ark Lab, Shengyu Zhu, Huawei Noah's Ark Lab, Bei Yu, The Chinese University of Hong Kong, Pengyun Li, HiSilicon, Cheng Chen, HiSilicon, Yu Huang, Mentor, A Siemens Business, Jianye Hao, Huawei Noah's Ark Lab
  • When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning
    Hao Geng, The Chinese University of Hong Kong, Fan Yang, Fudan University, Xuan Zeng, Fudan University, Bei Yu, The Chinese University of Hong Kong
9:45 - 10:30 am SESSION 6D | TUTORIAL: Ferroelectric FET Technologies and Its Applications: from Device to System
Moderator: Xunzhao Yin, Zhejiang University, Cheng Zhuo, Zhejiang University
  • Ferroelectric FET Technology and Applications: From Devices to Systems - Overview
    Cheng Zhuo, Zhejiang University
  • Ferroelectric FET Technology and Applications: From Devices to Systems - Device Modeling
    Kai Ni, Rochester Institute of Technology
  • Ferroelectric FET Technology and Applications: From Devices to Systems - Device-Circuit Co-Optimization
    Hussam Amrouch, University of Stuttgart
  • Ferroelectric FET Technology and Applications: From Devices to Systems - Cross-Layer Evaluation
    Xiaobo Sharon Hu, University of Notre Dame

SESSION 7
10:30 - 11:00 am SESSION 7A | In-Memory Computing Circuits and Architectures
Moderator: Marc Riedel, University of Minnesota, Twin Cities
  • Quarry: Quantization-based ADC Reduction for ReRAM-based Deep Neural Network Accelerators
    Azat Azamat, Ulsan National Institute of Science and Technology, Faaiz Asim, Ulsan National Institute of Science and Technology, Jongeun Lee, Ulsan National Institute of Science and Technology
  • Peripheral Circuitry Assisted Mapping Framework for Resistive Logic-In-Memory Computing
    Shuhang Zhang, Technical University of Munich, Hai (Helen) Li, Duke University, Ulf Schlichtmann, Technical University of Munich
  • Hybrid Analog-Digital In-Memory Computing
    Muhammad Rashedul Haq Rashed, University of Central Florida, Sumit Kumar Jha, University of Texas at San Antonio, Rickard Ewetz, University of Central Florida
10:30 - 11:00 am SESSION 7B | Techniques Towards Fully Automated Analog IC Designs
Moderator: Nuno Horta, University of Lisbon
  • From Specification to Topology: Automatic Power Converter Design via Reinforcement Learning
    Shaoze Fan, New Jersey Institute of Technology, Ningyuan Cao, Georgia Institute of Technology, Shun Zhang, New Jersey Institute of Technology, IBM, Jing Li, New Jersey Institute of Technology, Xiaoxiao Guo, IBM Research, Xin Zhang, IBM Research
  • From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning
    Juzheng Liu, University of Southern California, Shiyu Su, University of Southern California, Meghna Madhusudan, University of Minnesota, Mohsen Hassanpourghadi, University of Southern California, Samuel Saunders, University of Southern California, Qiaochu Zhang, University of Southern California, Rezwan Rasul, University of Southern California, Yaguang Li, Texas A&M University, Jiang Hu, Texas A&M University, Arvind Kumar Sharma, University of Minnesota, Sachin S. Sapatnekar, University of Minnesota, Ramesh Harjani, University of Minnesota, Anthony Levi, University of Southern California, Sandeep Gupta, University of Southern California, Mike Chen, University of Southern California
  • OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler
    Mingjie Liu, University of Texas Austin, Xiyuan Tang, University of Texas at Austin, Keren Zhu, University of Texas at Austin, Hao Chen, University of Texas at Austin, Nan Sun, University of Texas at Austin, David Z. Pan, University of Texas at Austin
10:30 - 11:00 am SPECIAL SESSION 7C | Big Data, Big Deal: Data Analysis and Smart Tuning of EDA Flows
Moderator: Iris Hui-Ru Jiang, National Taiwan University, Gi-Joon Nam, IBM Research
  • METRICS2.1 and Flow Tuning in the IEEE CEDA Robust Design Flow and OpenROAD
    Jinwook Jung, IBM Research, Andrew B. Kahng, University of California San Diego, Seungwon Kim, University of California San Diego, Ravi Varadarajan, University of California San Diego
  • Machine Learning Enhanced PPA Optimized Place and Route
    Paul Franzon, NC State University, W. Rhett Davis, NC State University, Rajeev Jain, Qualcomm, Luis Francisco, Synopsys, Billy Huggins, Synopsys
  • Online and Offline Machine Learning for Industrial Design Flow Tuning
    Matthew Ziegler, IBM Research, Jihye Kwon, Columbia University, Hung-Yi Liu, Cadence Design Systems, Luca P. Carloni, Columbia University
  • Reinforcement Learning-Driven Optimization for Superior Performance, Power and Productivity
    Thomas Andersen, Synopsys, Siddhartha Nath, NVIDIA
10:30 - 11:00 am SESSION 7D | TUTORIAL on Optimizing and Mapping Quantum Algorithms to Quantum Computers in NISQ Era
Moderator: Rudy Raymond, IBM Research, Weiwen Jiang, George Mason University
  • Exploration of Quantum Neural Architecture by Mixing Quantum Neuron Designs
    Zhepeng Wang, George Mason University, Zhiding Liang, University of Notre Dame, Shanglin Zhou, University of Connecticut, Caiwen Ding, University of Connecticut, Yiyu Shi, University of Notre Dame, Weiwen Jiang, George Mason University
  • Optimal Qubit Mapping with Simultaneous Gate Absorption
    Bochen Tan, University of California Los Angeles, Jason Cong, University of California Los Angeles
  • Can Noise on Qubits Be Learned in Quantum Neural Network? A Case Study on QuantumFlow
    Zhiding Liang, University of Notre Dame, Zhepeng Wang, George Mason University, Junhuan Yang, University of New Mexico, Lei Yang, University of New Mexico, Yiyu Shi, University of Notre Dame, Weiwen Jiang, George Mason University
CADENCE
11:00 am - 12:00 pm SPONSOR'S SESSION 1 | Data Analytics and Machine Learning delivers a chip design productivity revolution
Speaker: Rod Metcalfe, Cadence Design Systems



Note Agenda time zone is UTC-7 / PDT (CALIFORNIA)
Start - end: 7:20 AM - 12:00 PM PDT (CALIFORNIA), 03:20 - 08:00 PM CET (GERMANY), 10:20 PM - 03:00 AM CST (CHINA)


TO THE TOP

WEDNESDAY, NOV 03, 2021


SESSION 8
7:20 - 8:00 am SESSION 8A | Acceleration methodologies for Reconfigurable Computing
Moderator: Sotirios Xydis, Harokopio University of Athens
  • Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAs
    Dajiang Liu, Chongqing University, Ting Liu, Chongqing University, Xingyu Mo, Chongqing University, Jiaxing Shang, Chongqing University, Jiang Zhong, Chongqing University, Shouyi Yin, Tsinghua University
  • GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs
    Yuwei Hu, Cornell University, Yixiao Du, Cornell University, Ecenur Ustun, Cornell University, Zhiru Zhang, Cornell University
  • Accelerating Framework of Transformer by Hardware Design and Model Compression Co-Optimization
    Panjie Qi, East China Normal University, Edwin Hsing-Mean Sha, East China Normal University, Qingfeng Zhuge, East China Normal University, Hongwu Peng, University of Connecticut, Shaoyi Huang, University of Connecticut, Zhenglun Kong, Northeastern University, Yuhong Song, East China Normal University, Bingbing Li, University of Connecticut
  • DALTA: A Decomposition-based Approximate Lookup Table Architecture
    Chang Meng, Shanghai Jiao Tong University, Zhiyuan Xiang, Shanghai Jiao Tong University, Niyiqiu Liu, Shanghai Jiao Tong University, Yixuan Hu, Peking University, Jiahao Song, Peking University, Runsheng Wang, Peking University, Ru Huang, Peking University, Weikang Qian, Shanghai Jiao Tong University
7:20 - 8:00 am SESSION 8B | SoC Security
Moderator: Darshana Jayasinghe, University of New South Wales
  • Aker: A Design and Verification Framework for Safe and Secure SoC Access Control
    Francesco Restuccia, Scuola Superiore Sant'Anna Pisa, Andres Meza, University of California, San Diego, Ryan Kastner, University of California, San Diego
  • Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs
    Mehran Goli, University of Bremen, Rolf Drechsler, University of Bremen/DFKI
  • iSTELLAR: intermittent Signature aTtenuation Embedded CRYPTO with Low-Level metAl Routing
    Jeremy Blackstone, University of California, San Diego, Debayan Das, Purdue University, Alric Althoff, University of California, San Diego, Shreyas Sen, Purdue University, Ryan Kastner, University of California, San Diego
  • ReIGNN: State Register Identification Using Graph Neural Networks for Circuit Reverse Engineering
    Subhajit Dutta Chowdhury, University of Southern California, Kaixin Yang, University of Southern California, Pierluigi Nuzzo, University of Southern California
7:20 - 8:00 am SESSION 8C | Placement Techniques for Advanced VLSI Technology
Moderator: Jinwook Jung, IBM Research
  • Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs
    Jai-Ming Lin, Department of Electrical Engineering, National Cheng Kung University, Chung-Wei Huang, Department of Electrical Engineering, National Cheng Kung University, Liang-Chi Zane, Department of Electrical Engineering, National Cheng Kung University, Min-Chia Tsai, Department of Electrical Engineering, National Cheng Kung University, Chen-Fa Tsai, Department of Physical Design Service, Global Unichip Corporation, Che-Li Lin, Department of Physical Design Service, Global Unichip Corporation
  • DAPA: A Dataflow-aware Analytical Placement Algorithm for Modern Mixed-size Circuit Designs
    Jai-Ming Lin, Department of Electrical Engineering, National Cheng Kung University, Wei-Fan Huang, Department of Electrical Engineering, National Cheng Kung University, Yao-Chieh Chen, Department of Electrical Engineering, National Cheng Kung University, Yi-Ting Wang, Department of Electrical Engineering, National Cheng Kung University, Po-Wen Wang, Department of Electrical Engineering, National Cheng Kung University
  • A Row-Based Algorithm for Non-Integer Multiple-Cell-Height Placement
    Zih-Yao Lin, National Taiwan University, Yao-Wen Chang, National Taiwan University
  • AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA
    Tingyuan Liang, The Hong Kong University of Science and Technology, Gengjie Chen, The Chinese University of Hong Kong, Jieru Zhao, Shanghai Jiao Tong University, Sharad Sinha, Indian Institute of Technology, Goa, Wei Zhang, The Hong Kong University of Science and Technology
7:20 - 8:00 am SPECIAL SESSION 8D | Hardware/software Co-design for Neuromorphic Computing
Moderator: Antonino Tumeo, Pacific Northwest National Laboratory, Vito Giovanni Castellana, Pacific Northwest National Laboratory, Marco Minutoli, Pacific Northwest National Laboratory
  • Top-Down Neuromorphic Hardware Co-Design via Machine Learning and Simulation (Talk only)
    Catherine Schuman, Oak Ridge National Laboratory
  • A Design Flow for Mapping Spiking Neural Networks to Many-Core Neuromorphic Hardware
    Shihao Song, Drexel University, M. Lakshmi Varshika, Drexel University, Anup Das, Drexel University, Nagarajan Kandasamy, Drexel University
  • Architecture Search for Neuromorphic Design (Talk Only)
    Hai (Helen) Li, Duke University
  • Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators
    Nicolas Bohm Agostini, Pacific Northwest National Laboratory, Northeastern University, Serena Curzel, Pacific Northwest National Laboratory, Politecnico di Milano, Ismet Dagli, Pacific Northwest National Laboratory, Colorado School of Mines, Shihao Song, Pacific Northwest National Laboratory, Drexel University, Ankur Limaye, Pacific Northwest National Laboratory, Cheng Tan, Pacific Northwest National Laboratory, Marco Minutoli, Pacific Northwest National Laboratory, Vito Giovanni Castellana, Pacific Northwest National Laboratory, Vinay Amatya, Pacific Northwest National Laboratory, Joseph Manzano, Pacific Northwest National Laboratory, Anup Das, Drexel University, Fabrizio Ferrandi, Politecnico di Milano, Antonino Tumeo, Pacific Northwest National Laboratory

KEYNOTE 3
8:00 - 9:00 am KEYNOTE 3
Moderator: Rolf Drechsler, University of Bremen / DFKI
  • RISC-V Is Inevitable
    David Patterson, University of California, Berkeley

SESSION 9
9:00 - 9:45 am SESSION 9A | System-Level Optimization of Machine Learning Applications Execution on Heterogeneous Computing Systems
Moderator: Mohamed Sabry, Nanyang Technological University
  • Massively Parallel Big Data Classification on a Programmable Processing In-Memory Architecture
    Yeseong Kim, Daegu Gyeongbuk Institute of Science and Technology, Mohsen Imani, University of California, Irvine, Saransh Gupta, University of California, San Diego, Minxuan Zhou, University of California, San Diego, Tajana Rosing, University of California, San Diego
  • Overcoming the Memory Hierarchy Inefficiencies in Graph Processing Applications
    Jilan Lin, University of California, Santa Barbara, Shuangchen Li, University of California, Santa Barbara, Yufei Ding, University of California, Santa Barbara, Yuan Xie, University of California, Santa Barbara
  • Improving Inter-kernel Data Reuse With CTA-Page Coordination in GPGPU
    Xuanyi Li, National University of Defense Technology, Chen Li, National University of Defense Technology, Yang Guo, National University of Defense Technology, Rachata Ausavarungnirun, King Mongkut’s University of Technology North Bangkok
  • ScaleDNN: Data Movement Aware DNN Training on Multi-GPU
    Weizheng Xu, University of Pittsburgh, Ashutosh Pattnaik, Penn State University, Geng Yuan, Northeastern University, Yanzhi Wang, Northeastern University, Youtao Zhang, University of Pittsburgh, Xulong Tang, University of Pittsburgh
9:00 - 9:45 am SESSION 9B | Coming to Your Chips: NVM & Optical Interconnects
Moderator: Dharanidhar Dang, University of California San Diego
  • SSR: A Skeleton-based Synthesis Flow for Hybrid Processing-in-RRAM Modes
    Feng Wang, Peking University, Guangyu Sun, Peking University, Guojie Luo, Peking University
  • MORE2: Morphable Encryption and Encoding for Secure NVM
    Wei Zhao, Huazhong University of Science and Technology, Dan Feng, Huazhong University of Science and Technology, Yu Hua, Huazhong University of Science and Technology, Wei Tong, Huazhong University of Science and Technology, Jingning Liu, Huazhong University of Science and Technology, Jie Xu, Huazhong University of Science and Technology, Chunyan Li, Huazhong University of Science and Technology, Gaoxiang Xu, Huazhong University of Science and Technology, Yiran Chen, Duke University
  • ToPro: A Topology Projector and Waveguide Router for Wavelength-Routed Optical Networks-on-Chip
    Zhidan Zheng, Technical University of Munich, Mengchu Li, Technical University of Munich, Tsun-Ming Tseng, Technical University of Munich, Ulf Schlichtmann, Technical University of Munich
  • Traffic-Adaptive Power Reconfiguration for Energy-Efficient and Energy-Proportional Optical Interconnects
    Yuyang Wang, University of California, Santa Barbara, Kwang-Ting Cheng, Hong Kong University of Science and Technology
9:00 - 9:45 am SESSION 9C | Clock tree synthesis, placement, and routing - how to get the best results from the backend of the flow
Moderator: Nima Karimpour Darav, Xilinx, Inc.
  • Starfish: An Efficient P&R Co-Optimization Engine with A-based Partial Rerouting
    Fangzhou Wang, The Chinese University of Hong Kong, Lixin Liu, The Chinese University of Hong Kong, Jingsong Chen, The Chinese University of Hong Kong, Jinwei Liu, The Chinese University of Hong Kong, Xinshi Zang, The Chinese University of Hong Kong, Martin Wong, The Chinese University of Hong Kong
  • An OCV-Aware Clock Tree Synthesis Methodology
    Necati Uysal, University of Central Florida, Rickard Ewetz, University of Central Florida
  • Automatic Routability Predictor Development Using Neural Architecture Search
    Chen-Chia Chang, Duke University, Jingyu Pan, Duke University, Tunhou Zhang, Duke University, Zhiyao Xie, Duke University, Jiang Hu, Texas A&M University, Weiyi Qi, Cadence, Chung-Wei Lin, National Taiwan University, Ronjian Liang, Texas A&M University, Joydeep Mitra, Cadence, Elias Fallon, Cadence, Yiran Chen, Duke University
  • Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning
    Yi-Chen Lu, Georgia Institute of Technology, Siddhartha Nath, NVIDIA, Vishal Khandelwal, Synopsys Inc., Sung Kyu Lim, Georgia Tech
9:00 - 9:45 am SPECIAL SESSION 9D | Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures
Moderator: Jian-Jia Chen, TU Dortmund
  • Realizing Brain-Inspired Computing with Emerging Ferroelectric Transistors
    Hussam Amrouch, University of Stuttgart, Jian-Jia Chen, TU Dortmund, Mikail Yayla, TU Dortmund
  • Brain-Inspired Computing with Phase-Change Photonic Devices: Opportunities and Challenges
    Kaushik Roy, Indranil Chakraborty, Cheng Wang, Purdue University
  • Brain-Inspired Computing: Algorithm, Technology, and Application-Driven Innovations
    Yuan Xie, University of California, Santa Barbara, Fengbin Tu, University of California, Santa Barbara, Wenqin Huangfu, University of California, Santa Barbara, Ling Liang, University of California, Santa Barbara

SESSION 10
9:45 - 10:30 am SESSION 10A | Pushing the Boundaries of Machine Learning and Synthesis
Moderator: Vinicius Possani, Synopsys
  • Sampling-Based Approximate Logic Synthesis: An Explainable Machine Learning Approach
    Wei Zeng, University of Wisconsin-Madison, Azadeh Davoodi, University of Wisconsin-Madison, Rasit Onur Topaloglu, IBM
  • RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis
    Yasasvi Peruvemba, Indian Institute of Technology Indore, Shubham Rai, Technische Universität Dresden, Kapil Ahuja, Indian Institute of Technology Indore, Akash Kumar, Technische Universität Dresden
  • Graph Learning-Based Arithmetic Block Identification
    Zhuolun He, The Chinese University of Hong Kong, Ziyi Wang, The Chinese University of Hong Kong, Chen Bai, The Chinese University of Hong Kong, Haoyu Yang, NVIDIA Corp., Bei Yu, The Chinese University of Hong Kong
  • A Circuit-Based SAT Solver for Logic Synthesis
    He-Teng Zhang, National Taiwan University, Jie-Hong Roland Jiang, National Taiwan University, Alan Mishchenko, University of California Berkeley
9:45 - 10:30 am SESSION 10B | Hardware Approaches for Embedded Performance and Robustness
Moderator: Weiwen Jiang, George Mason University
  • Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FPGAs
    Shiqing Li, Nanyang Technological University, Di Liu, Nanyang Technological University, Weichen Liu, Nanyang Technological University
  • Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems
    Kazi Asifuzzaman, Barcelona Supercomputing Center (BSC), Mohamed Abu El Ala, McMaster University, Mohamed Hassan, McMaster University, Francisco J. Cazorla, Barcelona Supercomputing Center
  • dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference
    Elias Trommer, Infineon Technologies AG, Bernd Waschneck, Infineon Technologies AG, Akash Kumar, Technische Universität Dresden
  • Improving the Robustness of Redundant Execution with Register File Randomization
    Ilya Tuzov, Universidad Politécnica de Valencia, Pablo Andreu, Universidad Politécnica de Valencia, Laura Medina, Universidad Politécnica de Valencia, Tomas Picornell, Universidad Politécnica de Valencia, Antonio Robles, Universidad Politécnica de Valencia, Pedro Lopez, Universidad Politécnica de Valencia, Jose Flich, Universidad Politécnica de Valencia, Carles Hernández, Universidad Politécnica de Valencia
9:45 - 10:30 am SESSION 10C | Advanced Design Verification Methods
Moderator: Masahiro Fujita, University of Tokyo
  • Bounded Model Checking of Speculative Non-Interference
    Emmanuel Pescosta, TU Wien, Georg Weissenbacher, TU Wien, Florian Zuleger, TU Wien
  • Compatible Equivalence Checking of X-Valued Circuits
    Yu-Neng Wang, National Taiwan University, Yun-Rong Luo, National Taiwan University, Po-Chun Chien, National Taiwan University, Ping-Lun Wang, National Taiwan University, Hao-Ren Wang, National Taiwan University, Wan-Hsuan Lin, National Taiwan University, Jie-Hong Roland Jiang, National Taiwan University, Chung-Yang Huang, National Taiwan University
  • Feedback-Guided Circuit Structure Mutation for Testing Hardware Model Checkers
    Chengyu Zhang, East China Normal University, Minquan Sun, East China Normal University, Jianwen Li, East China Normal University, Ting Su, East China Normal University, Geguang Pu, East China Normal University
  • AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow
    Bulbul Ahmed, University of Florida, Fahim Rahman, University of Florida, Nick Hooten, Dynetics, Farimah Farahmandi, University of Florida, Mark Tehranipoor, University of Florida
9:45 - 10:30 am SPECIAL SESSION 10D | Security Closure of Physical Layouts
Moderator: Ramesh Karri, New York University
  • Secure back-end chip design? Why?
    Shekhar Borkar, Qualcomm
  • Reimagining Physical Design Security
    Serge Leef, DARPA
  • Security Closure for Physical Layouts
    Johann Knechtel, NYU Abu Dhabi

SESSION 11
10:30 - 11:00 am SPECIAL SESSION 11A | Harnessing the Power of Machine Learning: EDA to Accelerator Design
Moderator: Krishnendu Chakrabarty, Duke University
  • VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis
    Hadi Esmaeilzadeh, UC San Diego, Soroush Ghodrati, UC San Diego, Jie Gu, Northwestern University, Shiyu Guo, Northwestern University, Andrew B. Kahng, UC San Diego, Joon Kyung Kim, UC San Diego, Sean Kinzer, UC San Diego, Rohan Mahapatra, UC San Diego, Susmita Dey Manasi, University of Minnesota, Edwin Mascarenhas, UC San Diego, Sachin S. Sapatnekar, University of Minnesota, Ravi Varadarajan, UC San Diego, Zhiang Wang, UC San Diego, Hanyang Xu, UC San Diego, Brahmendra Reddy Yatham, UC San Diego, Ziqing Zeng, University of Minnesota
  • Optimizing VLSI Implementation with Reinforcement Learning
    Haoxing Ren, Nvidia, Saad Godil, Nvidia, Brucek Khailany, Nvidia, Robert Kirby, Nvidia, Haiguang Liao, Nvidia, Siddhartha Nath, NVIDIA, Jonathan Raiman, Nvidia, Rajarshi Roy, Nvidian
  • Heterogeneous Manycore Architectures Enabled by Processing-in-Memory for Deep Learning: From CNNs to GNNs
    Biresh Kumar Joardar, Duke University, Aqeeb Iqbal Arka, Washington State University, Janardhan Rao Doppa, Washington State University, Partha Pratim Pande, Washington State University, Hai (Helen) Li, Duke University, Krishnendu Chakrabarty, Duke University
10:30 - 11:00 am SESSION 11B | Parallel Power Grid Solver and Geometry-Based Techniques for Analog Circuit Design
Moderator: Ibrahim Elfadel, Khalifa University
  • pGRASS-Solver: A Parallel Iterative Solver for Scalable Power Grid Analysis Based on Graph Spectral Sparsification
    Zhiqiang Liu, Tsinghua University, Wenjian Yu, Tsinghua University
  • Performance-Aware Common-centroid Placement and Routing of Transistor Arrays in Analog Circuits
    Arvind Kumar Sharma, University of Minnesota, Meghna Madhusudan, University of Minnesota, Steven Burns, Intel Corporation, Soner Yaldiz, Intel Corporation, Parijat Mukherjee, Intel Corporation, Ramesh Harjani, University of Minnesota, Sachin S. Sapatnekar, University of Minnesota
  • CNN-Cap: Effective Convolutional Neural Network Based Capacitance Models for Full-Chip Parasitic Extraction
    Dingcheng Yang, Tsinghua University, Wenjian Yu, Tsinghua University, Yuanbo Guo, Tsinghua University, Wenjie Liang, Tsinghua University
10:30 - 11:00 am SESSION 11C | Reliability: From Interconnects to Systems
Moderator: Puneet Gupta, University of California, Los Angeles
  • Analytical Modeling of Transient Electromigration Stress based on Boundary Reflections
    Mohammad Abdullah Al Shohel, University of Minnesota, Vidya A. Chhabria, University of Minnesota, Nestor Evmorfopoulos, University of Thessaly, Sachin S. Sapatnekar, University of Minnesota
  • An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits
    Hao Zhang, Shanghai Jiao Tong University, Weifeng He, Shanghai Jiao Tong University, Yanan Sun, Shanghai Jiao Tong University, Mingoo Seok, Columbia University
  • Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits
    Marcello Traiola, Lyon Institute of Nanotechnology, Jorge Echavarria, Friedrich-Alexander-Universität Erlangen-Nürnberg FAU), Alberto Bosio, Lyon Institute of Nanotechnology, Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg FAU), Ian O'Connor, Lyon Institute of Nanotechnology
10:30 - 11:00 am SPECIAL SESSION 11D | 2021 CAD Contest at ICCAD
Moderator: Tsung-Wei Huang, University of Utah
  • Overview of 2021 CAD Contest at ICCAD
    Tsung-Wei Huang, University of Utah, Takashi Sato, Kyoto University, Chun-Yao Wang, National Tsing Hua University, Yu-Guang Chen, National Central University
  • 2021 ICCAD CAD Contest Problem A: Functional ECO with Behavioral Change Guidance and Benchmark Suite
    Yen-Chun Fang, Cadence Design Systems, Inc., Shao-Lun Huang, Cadence Design Systems, Inc, Chi-An Rocky Wu, Cadence Design Systems, Inc., Chung-Han Chou, Cadence Design Systems, Inc., Chih-Jen Jacky Hsu, Cadence Design Systems, Inc., Woei Tzy Wells Jong, Cadence Design Systems, Inc., Kei-Yong Khoo, Cadence Design Systems, Inc.
  • 2021 ICCAD CAD Contest Problem B: Routing with Cell Movement Advanced
    Kai-Shun Hu, Synopsys Inc., Tao-Chun Yu, Synopsys Inc., Ming-Jen Yang, Synopsys Inc., Chin-Fang Cindy Shen, Synopsys Inc.
  • 2021 ICCAD CAD Contest Problem C: GPU Accelerated logic rewriting
    Ghasem Pasandi, Nvidia, Sreedhar Pratty, Nvidia, David Brown, Nvidia, Yanqing Zhang, Nvidia, Haoxing Ren, Nvidia, Brucek Khailany, Nvidia
  • DATC RDF-2021: Design Flow and Beyond
    Jianli Chen, Fudan University, Iris Hui-Ru Jiang, Jiang National Taiwan University, Jinwook Jung, IBM, Seungwon Kim, University of California San Diego, Andrew B. Kahng, University of California San Diego, Victor N. Kravets, IBM, Yih-Lang Li, National Yang Ming Chiao Tung University, Ravi Varadarajan, University of California San Diego, Mingyu Woo, University of California San Diego
SYNOPSYS
11:00 am - 12:00 pm SPONSOR'S SESSION 2 | CAD for a More Secure Silicon Lifecycle
Speaker: Mike Borza, Synopsys



Note Agenda time zone is UTC-7 / PDT (CALIFORNIA)
Start - end: 6:00 AM - 01:05 PM PDT (CALIFORNIA), 02:00 - 09:05 PM CET (GERMANY), 09:00 PM - 04:05 AM (+1day) CST (CHINA)


TO THE TOP

THURSDAY, NOV 04, 2021


04:00 - 08:40 PM CET (GERMANY), 11:00 PM - 03:40 AM (+1day) CST (CHINA)
Organizers: Ibrahim (Abe) Elfadel, Khalifa University, Subhasish Mitra, Stanford University

03:20 - 09:30 PM CET (GERMANY), 10:20 PM - 04:30 AM (+1day) CST (CHINA)
Organizers: Alberto Bosio, École Centrale de Lyon, Alexandra Kourfali, University of Stuttgart, Alessandro Savino, Politecnico di Torino, Jürgen Teich, Friedrich-Alexander Universität Erlangen-Nürnberg (FAU)

04:20 - 09:05 PM CET (GERMANY), 11:20 PM - 04:05 AM (+1day) CST (CHINA)
Organizers: Yanzhi Wang, Northeastern University, Yingyan (Celine) Lin, Rice University

03:20 - 09:30 PM CET (GERMANY), 10:20 PM - 04:30 AM (+1day) CST (CHINA)
Organizers: Gang Qu, University of Maryland, College Park, Johanna Sepúlveda, Airbus Defence and Space

03:20 - 09:30 PM CET (GERMANY), 10:20 PM - 04:30 AM (+1day) CST (CHINA)
Organizers: Diana Göhringer, Technische Universität Dresden, Anton Klotz, Cadence Design Systems, Mark Willoughby, Europractice, Christian Sauer, Cadence Design Systems

06:00 - 10:00 PM CET (GERMANY), 01:00 - 05:00 AM (+1day) CST (CHINA)
Organizers: Matthew Guthaus, UC Santa Cruz, Jose Renau, UC Santa Cruz

03:00 - 10:00 PM CET (GERMANY), 10:00 PM - 05:00 AM (+1day) CST (CHINA)
Organizers: Mustafa Badaroglu, Qualcomm




Note Agenda time zone for FRIDAY is UTC+1 / CET (GERMANY)

TO THE TOP

FRIDAY, NOV 05, 2021


KEYNOTE 4
10:00 - 11:00 am KEYNOTE 4
Moderator: Sebastian Steinhorst, Technical University of Munich
  • Designing Reliable Distributed Systems
    Dirk Ziegenbein, Robert Bosch GmbH

11:00 - 11:30 am COFFEE BREAK

SESSION 12
11:30 am - 12:30 pm SESSION 12 | Security and System-Level CAD
Moderator: Daniel Tille, Infineon Technologies AG
  • BigIntegr: One-Pass Architectural Synthesis for Continuous-Flow Microfluidic Lab-on-a-Chip Systems
    Xing Huang, Technical University of Munich, Youlin Pan, Fuzhou University, Zhen Chen, Fuzhou University, Wenzhong Guo, Fuzhou University, Robert Wille, Johannes Kepler University Linz, Tsung-Yi Ho, National Tsing Hua University, Ulf Schlichtmann, Technical University of Munich
  • dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference
    Elias Trommer, Infineon Technologies AG, Bernd Waschneck, Infineon Technologies AG, Akash Kumar, Technische Universität Dresden
  • Engineering an Efficient Boolean Functional Synthesis Engine
    Priyanka Golia, Indian Institute of Technology Kanpur, National University of Singapore, Friedrich Slivovsky, TU Wien, Subhajit Roy, Indian Institute of Technology Kanpur, Kuldeep S. Meel, National University of Singapore
  • LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs
    Hassan Nassar, Karlsruher Institut für Technologie, Hanna Al Zughbi, Independent, Dennis Gnad, Karlsruher Institut für Technologie, Lars Bauer, Karlsruher Institut für Technologie, Mehdi Tahoori, Karlsruher Institut für Technologie, Jörg Henkel, Karlsruher Institut für Technologie
  • Aker: A Design and Verification Framework for Safe and Secure SoC Access Control
    Francesco Restuccia, Scuola Superiore Sant'Anna Pisa, Andres Meza, University of California, San Diego, Ryan Kastner, University of California, San Diego
  • RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis
    Yasasvi Peruvemba, Indian Institute of Technology Indore, Shubham Rai, Technische Universität Dresden, Kapil Ahuja, Indian Institute of Technology Indore, Akash Kumar, Technische Universität Dresden

12:30 - 1:30 pm LUNCH BREAK

SESSION 13
1:30 - 2:30 pm SESSION 13 | Back to the Future: EDA for Emerging Technologies
Moderator: Stephan Eggersglüß, Siemens Digital Industries Software
  • Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies
    Andreas Krinke, Technische Universität Dresden, Shubham Rai, Technische Universität Dresden, Akash Kumar, Technische Universität Dresden, Jens Lienig, Technische Universität Dresden
  • Peripheral Circuitry Assisted Mapping Framework for Resistive Logic-In-Memory Computing
    Shuhang Zhang, Technical University of Munich, Hai (Helen) Li, Duke University, Ulf Schlichtmann, Technical University of Munich
  • Optimal Mapping for Near-Term Quantum Architectures based on Rydberg Atoms
    Sebastian Brandhofer, University of Stuttgart, Hans Peter Büchler, University of Stuttgart, Ilia Polian, University of Stuttgart
  • ToPro: A Topology Projector and Waveguide Router for Wavelength-Routed Optical Networks-on-Chip
    Zhidan Zheng, Technical University of Munich, Mengchu Li, Technical University of Munich, Tsun-Ming Tseng, Technical University of Munich, Ulf Schlichtmann, Technical University of Munich
  • Manufacturing Cycle-Time Optimization Using Gaussian Drying Model for Inkjet-Printed Electronics
    Tsun-Ming Tseng, Technical University of Munich, Meng Lian, Technical University of Munich, Mengchu Li, Technical University of Munich, Philipp Rinklin, Technical University of Munich, Leroy Grob, Technical University of Munich, Bernhard Wolfrum, Technical University of Munich, Ulf Schlichtmann, Technical University of Munich
2:30 - 3:30 pm POSTER SESSION & NETWORKING BREAK

3:30 - 4:30 pm PANEL
Organizer: Georg Sigl, Technical University of Munich
  • Security meets Open-Source Hardware and Tools: Friend or Foe?
With the rise of RISC-V open-source hardware has become reality. Not just the architecture but also designs are developed open source. This means that at least RTL-code is publicly available. With open-source tools and libraries even lower levels of design data will become public. This can, on the one hand, jeopardize hiding attempts for cryptographic keys or put ideal attack locations on the spot, thus compromising security. On the other hand, development of open-source hardware trust anchors increases the availability of such IP cores and allows integration in system-on-chips (SoC), thus improving security of future products. There they can be used, e.g., to ensure secure boot processes, protect software updates, and cryptographic authentication of these SoCs. Open source allows security verification for everybody and therefore improves transparency and trust in such hardware trust anchors. At the same time, it has a significant impact on the business for semiconductor vendors offering such trust anchors as dedicated chips.
The panel aims to discuss the impact of open-source hardware on the business, technical sovereignty, security and tries to identify the trends for the next years. The panelists cover the complete industrial value chain of trusted electronics and research in the area of secure hardware as well as tools.

Panelists:
  • Sascha Kegreiss, HENSOLDT Cyber
  • Johanna Sepúlveda, Airbus Defence and Space
  • Ilia Polian, University of Stuttgart
  • Johann Heyszl, Fraunhofer AISEC

4:30 - 5:30 pm INDUSTRY-ACADEMIA NETWORKING SESSION
Moderator: Ulf Schlichtmann, Technical University of Munich
  • Future of Academia-Industry Engagement in EDA for Research and Education
Panelists:
  • Anton Klotz, Cadence Design Systems
  • Patrick Haspel, Synopsys
  • Frank Schenkel, MunEDA
  • Raik Brinkmann, Siemens AG
5:30 - 6:30 pm CLOSING & BUS TRANSFER TO RESTAURANT

7:00 - 10:00 pm SOCIAL DINNER & NETWORKING




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