2019 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 4-7, 2019The Westin Westminster Westminster, CO



PaperID PaperTitle
14 GPU Acceleration of RSA is Vulnerable to Side-channel Timing Attacks
22 LeapChain: Efficient Blockchain Verification for Embedded IoT
36 SODA: Stencil with Optimized Dataflow Architecture
39 Achieving Fast Sanitization with Zero Live Data Copy for MLC Flash Memory
40 Steep Coverage-Ascent Directed Test Generation for Shared-Memory Verification of Multicore Chips
42 HISA: Hardware Isolation-based Secure Architecture for CPU-FPGA Embedded Systems
45 Effective Simple-Power Analysis Attacks of Elliptic Curve Cryptography on Embedded Systems
46 HLSPredict: Cross Platform Performance Prediction for FPGA High-Level Synthesis
47 A Fast Thermal-Aware Fixed-Outline Floorplanning Methodology Based on Analytical Models
51 Tetris: Re-architecting Convolutional Neural Network Computation for Machine Learning Accelerators
52 Modeling and Optimization of Magnetic Core TSV-Inductor for On-Chip DC-DC Converter
56 RFUZZ: Coverage-Directed Fuzz Testing of RTL on FPGAs
65 Macro-Aware Row-Style Power Delivery Network Design for Better Routability
67 An Efficient Data Reuse Strategy for Multi-Pattern Data Access
83 A Formal Instruction-Level GPU Model for Scalable Verification
103 Physical modeling of bitcell stability in subthreshold SRAMs for leakage-area optimization under PVT variations
106 3DICT: A Reliable and QoS Capable Mobile Process-In-Memory Architecture for Lookup-based CNNs in 3D XPoint ReRAMs
109 A Ferroelectric FET based Power-efficient Architecture for Data-intensive Computing
113 Uncertainty Quantification of Electronic and Photonic ICs with Non-Gaussian Correlated Process Variations
117 TGPA: Tile-Grained Pipeline Architecture for Low Latency CNN Inference
121 Aliens: A Novel Hybrid Architecture for Resistive Random-Access Memory
123 NID: Processing Binary Convolutional Neural Network in Commodity DRAM
127 Adaptive-Precision Framework for SGD using Deep Q-Learning
129 Design and Algorithm for Clock Gating and Flip-flop Co-optimization
133 RAPID: Read Acceleration for Improved Performance and Endurance in MLC/TLC NVMs
150 PolySA: Polyhedral-Based Systolic Array Auto-Compilation
167 TimingSAT: Timing Profile Embedded SAT Attack
181 Defensive Dropout for Hardening Deep Neural Networks under Adversarial Attacks
186 RouteNet: Routability Prediction for Mixed-Size Designs Using Convolutional Neural Network
203 Differentiated Handling of Physical Scenes and Virtual Objects for Mobile Augmented Reality
204 A Practical Detailed Placement Algorithm under Multi-Cell Spacing Constraints
208 Mixed-Cell-Height Placement Considering Drain-to-Drain Abutment
209 Sneak Path Free Reconfiguration of Via-switch Crossbars Based FPGA
211 Efficient Hardware Acceleration of CNNs using Logarithmic Data Representation with Arbitrary log-base
215 Analytical Solution of Poisson's Equation and Its Application to VLSI Global Placement
218 Mixed-Cell-Height Placement with Complex Minimum-Implant-Area Constraints
227 C-GOOD: C-code Generation Framework for Optimized On-device Deep Learning
229 DALS: Delay-driven Approximate Logic Synthesis
230 Extending ML-OARSMT to Net Open Locator with Efficient and Effective Boolean Operations
235 Electromagnetic Equalizer: An Active Countermeasure Against EM Side-channel Attack
236 DL-RSIM: A Simulation Framework to Enable Reliable ReRAM-based Accelerators for Deep Learning
245 Design Space Exploration of Multi-output Logic Function Approximations
246 Canonicalization of Threshold Logic Representation and Its Applications
249 AXNet: ApproXimate computing using an end-to-end trainable neural network
251 Logic Synthesis of Binarized Neural Networks for Efficient Circuit Implementation
254 Co-Manage Power Delivery and Consumption for Manycore Systems Using Reinforcement Learning
258 Mixed-Cell-Height Legalization Considering Technology and Region Constraints
259 Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors
261 Mixed Size Crossbar based RRAM CNN Accelerator with Overlapped Mapping Method
269 Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects
279 An Algorithm for Initial Detailed Routing
285 FCN-Engine: Accelerating Deconvolutional Layers in Classic CNN Processors
288 Industrial Experiences with Resource Management under Software Randomization in ARINC653 Avionics Environments
289 Simultaneous Partitioning and Signals Grouping for Time-Division Multiplexing in 2.5D FPGA-Based Systems
303 CustomTopo: A Topology Generation Method for Application-Specific Wavelength-Routed Optical NoCs
304 Enhancing the Solution Quality of Hardware Ising-Model Solver via Parallel Tempering
309 Best of Both Worlds: Integration of Split Manufacturing and Camouflaging into a Security-Driven CAD Flow for 3D ICs
317 Wavefront-MCTS: Multi-objective Design Space Exploration of NoC Architectures based on Monte Carlo Tree Search
321 Property Specific Information Flow Analysis for Hardware Security Verification
334 DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs
340 Multi-Channel and Fault-Tolerant Control Multiplexing for Flow-Based Microfluidic Biochips
343 Machine-learning-based Dynamic IR Drop Prediction for ECO
345 AxBA: An Approximate Bus Architecture Framework
349 A Cross-Layer Methodology for Design and Optimization of Networks in 2.5D Systems
352 DIMA: A Depthwise CNN In-Memory Accelerator
360 Deterministic Methods for Stochastic Computing using Low-Discrepancy Sequences
364 SPN Dash – Fast Detection of Adversarial Attacks on Mobile via Sensor Pattern Noise Fingerprinting
376 Algorithm-Hardware Co-Design of Single Shot Detector for Fast Object Detection on FPGAs
377 PolyCleaner: Clean your Polynomials before Backward Rewriting to Verify Million-gate Multipliers
379 Scalable-Effort ConvNets for Multilevel Classification
381 Parallelizable Bayesian Optimization for Analog and Mixed-Signal Rare Failure Detection with High Coverage
392 Optimizing Data Layout and System Configuration on FPGA-based Heterogeneous Platforms
393 Fast FPGA Emulation of Analog Dynamics in Digitally-Driven Systems
400 Designing Adaptive Neural Networks for Energy-Constrained Image Classification
409 EMAT: An Efficient Multi-Task Architecture for Transfer Learning using ReRAM
412 Remote Inter-Chip Power Analysis Side-Channel Attacks at Board-Level
418 Architecting Data Placement in SSDs for Efficient Secure Deletion Implementation
420 SCADET: A Side-Channel Attack Detection Tool for Tracking Prime+Probe
429 LiteHAX: Lightweight Hardware-Assisted Attestation of Program Execution
442 SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints
444 FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design
447 Watermarking Deep Neural Networks for Embedded Systems
448 Invocation-driven Neural Approximate Computing with aMulticlass-Classifier and Multiple Approximators
452 [Anonymous]: An Initial Detailed Router for Advanced VLSI Technologies
459 Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction
460 High-Level Synthesis with Static Timing-Sensitive Information Flow Enforcement
465 FELIX: Fast and Energy-Efficient Logic in Memory
466 Shadow Attacks on MEDA Biochips
467 Transient Circuit Simulation using Matrix Exponential for Differential Algebraic Systems
469 Unlocking Fine-Grain Parallelism for AIG Rewriting
470 Strain-Aware Performance Evaluation and Correction for OTFT-Based Flexible Displays
479 HLS-based Optimization and Design Space Exploration for Applications with Variable Loop Bounds
489 Design and Optimization of Edge Computing Distributed Neural Processor for Biomedical Rehabilitation with Sensor Fusion
513 IC/IP Piracy Assessment of Reversible Logic
523 DeepFense: Real-time Defense against Adversarial Deep Learning
530 SWAN: Mitigating Hardware Trojans with Design Ambiguity
534 Online Human Activity Recognition using Low-Power Wearable Devices
538 Area-efficient Low-power Face-to-Face-bonded 3D Liquid State Machine Design in the Internet-of-Things Era