2017 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 13-16, 2017Irvine Marriott Irvine, CA

CONGRATULATIONS TO THE 2017 ACCEPTED PAPERS!

 

Paper ID Title
6 Thermal Modeling and Design on Smartphones with Heat Pipe Cooling Technique
12 SIMPLE MAGIC: Synthesis and In-memory MaPping of Logic Execution for Memristor Aided loGIC
14 Leveraging Value Locality for Efficient Design of a Hybrid Cache in Multicore Processors
20 Efficient Programming of Reconfigurable Radio Frequency (RF) Systems
33 NEMESIS: A Software Approach for Computing in Presence of Soft Errors
39 Fast Physics-based Electromigration Analysis for Multi-Branch Interconnect Trees
46 Scalable N-worst Algorithms for Dynamic Timing and Activity Analysis
51 HLS-Insight: Fast and Accurate Performance Estimation for FPGA HLS
52 Switch Cell Optimization of Power-gated Modern System-on-Chips
64 Power Grid Verification Under Transient Constraints
66 Data Path Optimisation and Delay Matching for Asynchronous Bundled-Data Balsa Circuits
67 Rapid Gate Sizing with Fewer Iterations of Lagrangian Relaxation
75 PRESCOTT: Preset-based Cross-Point Architecture for Spin-Orbit-Torque Magnetic Random Access Memory
79 IR-drop aware Design & Technology Co-Optimization for N5 node with different device and cell height options
85 Online Message Delay Prediction for Model Predictive Control over Controller Area Network
96 Hardening Extended Memory Access Control Schemes with Self-Verified Address Spaces
100 Blockage-Aware Terminal Propagation for Placement Wirelength Minimization
107 Design of Accurate Stochastic Number Generators with Noisy Emerging Devices for Stochastic Computing
108 Cross-program Design Space Exploration by Ensemble Transfer Learning
109 Advanced Datapath Synthesis using Graph Isomorphism
113 Early SoC Security Validation by VP-based Static Information Flow Analysis
121 Online and Incremental Machine Learning Approaches for IC Yield Improvement
123 RRAM-based Reconfigurable In-Memory Computing Architecture with Hybrid Routing
130 Fast Physics-Based Electromigration Assessment by Efficient Solution of Linear Time-Invariant (LTI) Systems
133 Fault Injection Attack on Deep Neural Network
147 VST: A Virtual Stress Testing Framework for Discovering Bugs in SSD Flash-Translation Layers
154 Mining Mutation Testing Simulation Traces for Security and Testbench Debugging
156 Approximating Complex Arithmetic Circuits with Formal Error Guarantees: 32-bit Multipliers Accomplished
158 Accelerating Functional Timing Analysis with Encoding Duplication Removal and Redundant State Propagation
169 An Open Benchmark Implementation for Multi-CPU Multi-GPU Pedestrian Detection in Automotive Systems
171 Computationally Efficient Standard-Cell FEM-based Thermal Analysis
175 Enabling Exact Delay Synthesis
176 A Load Balancing Inspired Parallel Execution Optimization Framework for Many-core Systems
178 Learn-on-the-Go: Autonomous Cross-Subject Context Learning for Internet-of-Things Applications
182 A streaming clustering approach using a heterogeneous system for big data analysis
187 Towards Reliability-Aware Circuit Design in Nanoscale FinFET Technology — New-Generation Aging Model and Circuit Reliability Simulator
191 DtCraft: A Distributed Execution Engine for Compute-intensive Applications
194 Reverse Engineering Camouflaged Sequential Circuits Without Scan Access
197 Virtual Persistent Cache: Remedy the Long Latency Behavior of Host-Aware Shingled Magnetic Recording Drives
199 GRASP based Metaheuristics for Layout Pattern Classification
200 ApproxLUT: A Novel Approximate Lookup Table-Based Accelerator
201 ORCHARD: Visual Object Recognition Accelerator Based on Approximate In-Memory Processing
204 Speeding Up Crossbar Resistive Memory by Exploiting In-memory Data Patterns
205 Optimal Checkpointing for Secure Intermittently-Powered IoT Devices
208 P4: Phase-Based Power/Performance Prediction of Heterogeneous Systems via Neural Networks
215 Energy-Efficient, High-Performance, Highly-Compressed Deep Neural Network Design using Block-Circulant Matrices
223 Why You Should Care About Don't Cares: Exploiting Internal Don't Care Conditions for Hardware Trojans
251 Simultaneous Template Assignment and Layout Decomposition Using Multiple BCP Materials in DSA-MP Lithography
257 A Novel Damped-Wave Framework for Macro Placement
258 Exploring Cache Bypassing and Partitioning for MultiTasking on GPUs
263 An Integrated-Spreading-Based Macro-Refining Algorithm for Large-Scale Mixed-Size Circuit Designs
264 Sequential Engineering Change Order under Retiming and Resynthesis
267 Redistribution Layer Routing for Wafer-Level Integrated Fan-Out Package-on-Packages
271 Clock-Aware Placement for Large-Scale Heterogeneous FPGAs
273 Dedicated Synthesis for MZI-based Optical Circuits based on AND-Inverter Graphs
274 A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization
279 Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints
284 SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm
290 A Coordinated Synchronous and Asynchronous Parallel Routing Approach for FPGAs
291 Thermosiphon: A Thermal Aware NUCA Architecture for Write Energy Reduction of the STT-MRAM based LLCs
296 TraNNsformer: Neural Network Transformation for Efficient Crossbar Based Neuromorphic System Design
304 SAMG: Sparsified Graph Theoretic Algebraic Multigrid for Solving Large Symmetric Diagonally Dominant (SDD) Matrices
318 Power Scheduling with Active Power Grids
319 Towards Warp-Scheduling Friendly STT-MRAM/SRAM Hybrid GPGPU Register File Design
320 Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques
329 Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging
330 Statistically Certified Approximate Logic Synthesis
334 AEP: An Error-bearing Neural Network Accelerator for Energy Efficiency and Model Protection
335 COMBA: A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications
344 An Automated SAT-based Method for the Design of On-Chip Bit-flip Detectors
353 A Novel Cache Bank Timing Attack
359 Making Split Fabrication Synergistically Secure and Manufacturable
363 A Novel Two-stage Modular Multiplier Based on Racetrack Memory for Asymmetric Cryptography
367 Approximate Image Storage with Multi-level Cell STT-MRAM Main Memory
370 Exploring the Exponential Integrators with Krylov Subspace Algorithms for Nonlinear Circuit Simulation
373 DAGSENS: Directed Acyclic Graph Based Direct and Adjoint Transient Sensitivity Analysis for Event-Driven Objective Functions
377 Stress-Aware Performance Evaluation of 3D-Stacked Wide I/O DRAMs
386 Adaptive Error Recovery in MEDA Biochips Based on Droplet-Aliquot Operations and Predictive Analysis
387 CycSAT: SAT-Based Attack on Cyclic Logic Encryptions
389 State Retention for Power Gated Design with Non-Uniform Multi-Bit Retention Registers
390 Threshold-based Obfuscated Keys with Quantifiable Security against Invasive Readout
400 Front-End-of-Line Attacks in Split Manufacturing
401 MeDNN: A Distributed Mobile System with Enhanced Partition and Deployment for Large-Scale DNNs
409 AdaLearner: An Adaptive Distributed Mobile Learning System for Neural Networks
422 Cost-Effective Design of Scalable High Performance Systems using Active and Passive Interposers
423 ACE: Adaptive Channel Estimation for Detecting Analog/RF Trojans in WLAN Transceivers
437 A Case for Low Frequency Single Cycle Multi Hop NOCs for Energy Efficiency and High Performance
442 Sortex: Efficient Timing-Driven Synthesis of Reconfigurable Flow-Based Biochips for Scalable Single-Cell Screening
456 SMARTER: Secure Remote Runtime Attestation Resilient against Memory Attacks
466 Cost-Effective Write Disturbance Mitigation Techniques for Advancing PCM Density
467 Optimal Multi-Row Detailed Placement for Yield and Model-Hardware Correlation Improvements in Sub-10nm VLSI
473 A Closed-loop Design to Enhance Weight Stability of Memristor Based Neural Network Chips
478 Dynamic Partitioning to Mitigate Stuck-at Faults in Emerging Memories
499 A Spike-Based Long Short-Term Memory on a Neurosynaptic Processor
506 Safety model checking with complimentary approximations
509 Memristor-Based Perceptron Classifier: Increasing Complexity and Coping with Imperfect Hardware
510 Supporting Hardware Reusability: Construction Languages, Compiler Frameworks, and Transformations
518 Clepsydra: Modeling Timing Flows in Hardware Designs
528 MT-Spike: A Multilayer Time-based Spiking Neuromorphic Architecture with Temporal Error Backpropagation
531 Energy efficient runtime approximate computing on data flow graphs
532 SAT-Based Compilation to a non-vonNeumann Processor
534 ACQUA: Adaptive and Cooperative Quality-Aware Control for Automotive Cyber-Physical Systems
535 Hybrid State Machine Model for Fast Model Predictive Control: Application to Path Tracking
538 Efficient Simulation of EM Side-Channel Attack Resilience
542 Near Optimal Energy Allocation for Self-Powered Wearable Systems