2018 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 5-8, 2018Hilton San Diego Resort & Spa San Diego, CA

Congratulations 2016 Accepted Papers!

2017 Accepted Papers
29
Incorporating Cut Redistribution with Mask Assignment to Enable 1D Gridded Design
43
Efficient Memory Compression in Deep Neural Networks Using Coarse-Grain Sparsification for Speech Applications
46
Making Split-Fabrication More Secure
47
KCAD: Kinetic Cyber Attack Detection Method for Cyber-Physical Additive Manufacturing Systems
50
Generation and Use of Statistical Timing Macro-models considering Slew and Load Variability
51
Autonomous Sensor-Context Learning in Dynamic Human-Centered Internet-of-Things Environments
53
An Efficient and Accurate Algorithm for Computing RC Current Response with Applications to EM Reliability Evaluation
60
OWARU: Free-Space-Aware Timing-Driven Incremental Placement
64
Delay-Optimal Technology Mapping for In-Memory Computing using ReRAM Devices
69
Efficient Yield Estimation through Generalized Importance Sampling with Application to NBL-Assisted SRAM bitcells
73
Arbitrary Streaming Permutations with Minimum Memory and Latency
76
RC-Aware Global Routing
80
Parallel Code-Specific CPU Simulation with Dynamic Phase Convergence Modeling for HW/SW Co-Design
81
A Deterministic Approach to Stochastic Computation
86
Design of Power-Efficient Approximate Multipliers for Approximate Artificial Neural Network
89
TinySPICE Plus: Scaling Up Statistical SPICE Simulations on GPU Leveraging Shared-Memory Based Sparse Matrix Solution Techniques
92
Efficient Synthesis of Graph Methods: a Dynamically Scheduled Architecture
98
Fast Generation of Lexicographic Satisfiable Assignments: Enabling Canonicity in SAT-based Applications
100
Efficient and Accurate Analysis of Single Event Transients Propagation Using SMT-Based Techniques
103
Fast Physics-Based Electromigration Checking for On-Die Power Grids
104
Duplex: Simultaneous Parameter-Performance Exploration for Optimizing Analog Circuits
110
A Fast Layer Elimination Approach for Power Grid Reduction
111
Security of Neuromorphic Computing: Thwarting Learning Attacks Using Memristor’s Obsolescence Effect
115
Control Synthesis and Delay Sensor Deployment for Efficient ASV Designs
116
Allocation of Multi-bit Flip-flops in Logic Synthesis for Power Optimization
124
Detailed Placement for Modern FPGAs using 2D Dynamic Programming
130
Joint Loop Mapping and Data Placement for Coarse-Grained Reconfigurable Architecture with Multi-bank Memory
131
Multi-bank Memory Optimization for Parallel Data Access in Multiple Data Arrays
141
DSA-compliant Routing for Two-dimensional Patterns Using Block Copolymer Lithography
143
A Novel Unified Dummy Fill Insertion Framework with SQP-Based Optimization Method
154
On Detecting Delay Anomalies Introduced by Hardware Trojans
155
NVsim-CAM: A Circuit-Level Simulator for Emerging Nonvolatile Memory based Content-Addressable Memory
168
Formulating Customized Specifications for Resource Allocation Problem of Distributed Embedded Systems
169
Scope - Quality Retaining Display Rendering Workload Scaling based on User-Smartphone Distance
170
BugMD: Automatic Mismatch Diagnosis for Bug Triaging
172
Compact Oscillation Neuron Exploiting Metal-Insulator-Transition for Neuromorphic Computing
175
CamoPerturb: Secure IC Camouflaging for Minterm Protection
183
Energy-efficient Fault Tolerance Approach for Internet of Things Applications
184
ODESY: a novel 3T-3MTJ cell design with Optimized area DEnsity, Scalability and latencY
197
VCR: Simultaneous Via-template and Cut-template-aware Routing for Directed Self-Assembly Technology
200
Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation
224
A New Tightly-Coupled Transient Electro-Thermal Simulation Method for Power Electronics
227
Critical Path Isolation for Time-to-Failure Extension and Lower Voltage Operation
230
Statistical Methodology to Identify Optimal Placement of On-Chip Process Monitors for Predicting Fmax
233
SAINT: Handling Module Folding and Alignment in Fixed-outline Floorplan for 3D ICs
238
Memsqueezer: Re-architecting the On-chip memory Sub-system of Deep Learning Accelerator for Embedded Devices
253
A Tensor-Based Volterra Series Black-Box Nonlinear System Identification And Simulation Framework
261
Enabling Online Learning in Lithography Hotspot Detection with Information-theoretic Feature Optimization
273
Redistribution Layer Routing for Integrated Fan-Out Wafer-Level Chip-Scale Packages
279
IC Thermal Analyzer for Versatile 3-D Structures Using Multigrid Preconditioned Krylov Methods
281
Compiled Symbolic Simulation for SystemC
288
Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip
290
A Hardware-based Technique for Efficient Implicit Information Flow Tracking
299
TASA: Toolchain-Agnostic Static Software Randomisation for Critical Real-Time Systems
301
Exploiting Ferroelectric FETs for Low-Power Non-Volatile Logic-in-Memory Circuits
302
Architectural-Space Exploration of Approximate Multipliers
323
Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow
324
Control-Fluidic CoDesign for Paper-Based Digital Microfluidic Biochips
329
Encasing Block Ciphers to Foil Key Recovery Attempts via Side Channel
330
An Optimization-Theoretic Approach for Attacking Physical Unclonable Functions
338
The Art of Semi-Formal Bug Hunting
340
BoostNoC: Power Efficient Network-on-Chip Architecture for Near Threshold Computing
341
Design Technology for Fault-Free and Maximally-Parallel Wavelength-Routed Optical Networks-on-Chip
357
Approximation-aware Rewriting of AIGs for Error Tolerant Applications
358
Exploiting Randomness in Sketching for Efficient Hardware Implementation of Machine Learning Applications
362
Approximation Knob: Power Capping Meets Energy Efficiency
371
A Data Locality-aware Design Framework for Reconfigurable Sparse Matrix-Vector Multiplication Kernel
373
MrDP: Multiple-row Detailed Placement of Heterogeneous-sized Cells for Advanced Nodes
376
QScale: Thermally-Efficient QoS Management on Heterogeneous Mobile Platforms
384
LRR-DPUF: Learning Resilient and Reliable Digital Physical Unclonable Function
397
Are Proximity Attacks a Threat to the Security of Split Manufacturing of Integrated Circuits?
399
Chip Editor: Leveraging Circuit Edit for Logic Obfuscation and Trusted Fabrication
401
Neural Networks Designing Neural Networks: Multi-Objective Hyper-Parameter Optimization
402
Synthesis of Statically Analyzable Accelerator Networks From Sequential Programs
412
PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model
418
Exact Diagnosis using Boolean Satisfiability
423
A Machine Learning Approach to Fab-of-Origin Attestation
430
Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
442
A Polyhedral Model-based Framework for Dataflow Implementation on FPGA devices of Iterative Stencil Loops
452
Reconfigurable In-Memory Computing with Resistive Memory Crossbar
458
Design Space Exploration of Drone Infrastructure for Large-Scale Delivery Services
463
Automated Error Prediction for Approximate Sequential Circuits
464
Scalable, High-Quality SAT-Based Multi-Layer Escape Routing
472
How Much Cost Reduction Justifies the Adoption of Monolithic 3D ICs at 7nm Node?
484
Provably Secure Camouflaging Strategy for IC Protection
487
A Flash-based Digital Circuit Design Flow
495
Analytic Approaches to the Collapse Operation and Equivalence Verification of Threshold Logic Circuits
513
Making neural encoding robust and energy-efficient: an advanced analog temporal encoder for brain-inspired computing systems
521
Improved Flop Tray-Based Design Implementation for Power Reduction
535
Splitting Functions in Code Management on Scratchpad Memories
541
Voltage-Based Electromigration Immortality Check for General Multi-Branch Interconnects
543
Multi-Objective Design Optimization for Flexible Hybrid Electronics
544
Imprecise Security: Quality and Complexity Tradeoffs for Hardware Information Flow Tracking
553
Tier Partitioning Strategy to Mitigate BEOL Degradation and Cost Issues in Monolithic 3D ICs
555
Cascade2D: A Design-Aware Partitioning Approach to Monolithic 3D IC with 2D Commercial Tools
556
Adaptive Performance Prediction for Integrated GPUs
565
Exploring Aging Deceleration in FinFET-Based Multi-Core Systems