2013 Paper Submission Call for Papers

Questions: Contact the Program Chair Yao-Wen Chang or Vice Program Chair Diana Marculescu

Deadline for Electronic Submission Of Abstracts:
Monday, April 1, 2013 - 5:00pm Pacific Daylight time (GMT-7)

Deadline for Electronic Submission Of Papers:
Monday, April 8, 2013 - 5:00pm Pacific Daylight time (GMT-7)

Original technical submissions on, but not limited to, the following topics are invited:

1.1 System Design:
• System-level specification, modeling, and simulation
• System design flows and methods
• HW/SW co-design, co-simulation, co-optimization, and co-exploration
• HW/SW platforms
• Rapid prototyping
• System design case studies and applications
• System-level issues for 3D integration
• Micro-architectural transformation
• Memory architecture and system synthesis
• System communication architecture
• Network-on-chip design methodologies and CAD
• Network-on-chip design case studies and prototyping
1.2 Embedded Systems Hardware: • Multi-core/multi-processors systems
• Heterogeneous embedded architectures
• HW/SW co-design for embedded systems
• Static and dynamic reconfigurable architectures
• Memory hierarchies and management
• Custom storage architectures (flash, phase change memory, STT-RAM, etc.)
• Application-specific instruction-set processors (ASIPs)
• Cyber-physical system architectures
1.3 Embedded Systems Software:
• Real-time software and operating systems
• Middleware and virtual machines
• Timing analysis and WCET
• Programming models for multi-core systems
• Profiling and compilation techniques
• Design exploration, synthesis, validation, verification, and optimization
• HW/SW security techniques
• Software for cyber-physical systems
1.4 Power and Thermal Considerations in System Design:
• Power and thermal estimation, analysis, optimization, and management techniques for hardware and software systems

2.1 High-Level, Behavioral, and Logic Synthesis and Optimization:
• High-level/Behavioral/Logic synthesis
• Technology-independent optimization and technology mapping
• Functional and logic timing ECO
• Resource scheduling, allocation, and synthesis
• Interaction between logic synthesis and physical design
2.2 Validation, Simulation, and Verification:
• High-level/Behavioral/Logic modeling and validation
• High-level/Behavioral/Logic simulation
• Formal, semi-formal, and assertion-based verification
• Equivalence and property checking
• Emulation and hardware simulation/acceleration
• Post-silicon functional validation
2.3 Cell-Library Design, Partitioning, Floorplanning, Placement:
• Cell-library design and optimization
• Transistor and gate sizing
• High-level physical design and synthesis
• Estimation and hierarchy management
• 2D and 3D partitioning, floorplanning, and placement
• Post-placement optimization
• Buffer insertion and interconnect planning
2.4 Clock Network Synthesis, Routing, and Post-Layout Optimization and Verification:
• 2D and 3D clock network synthesis
• 2D and 3D global and detailed routing
• Package-/Board-level routing and chip-package-board co-design
• Post-layout/-silicon optimization
• Physical verification and design rule checking

3.1 Design for Manufacturability:
• Process technology characterization, extraction, and modeling
• CAD for design/manufacturing interfaces
• CAD for reticle enhancement and lithography-related design
• Variability analysis and statistical design and optimization
• Yield estimation and design for yield
3.2 Design for Reliability:
• Analysis and optimization for reliability issues (thermal, electromigration, aging, stress, ESD, etc.)
• Design for resilience and robustness
• Soft errors
3.3 Testing:
• Digital fault modeling and simulation
• Delay, current-based, low-power test
• ATPG, BIST, DFT, and compression
• Memory test and repair
• Core, board, system, and 3D IC test
• Post-silicon validation and debug
• Analog, mixed-signal, and RF test

4.1 Timing, Power, and Power Networks:
• Deterministic and statistical static timing analysis and optimization
• Power and leakage analysis and optimization
• Low power design
• Power/ground network analysis and synthesis
4.2 Signal Integrity and Devices/Interconnect Modeling and Simulation:
• Signal integrity analysis and optimization
• Package modeling, analysis, and optimization
• EMI/EMC simulation and optimization
• Device, interconnect, and circuit modeling, extraction, and simulation
• Behavioral modeling of devices and circuits
4.3 Analog, Mixed-Signal, RF and Multi-Domain Design and CAD:
• System-level issues for analog, mixed-signal, and RF designs
• Synthesis and verification for analog, mixed-signal, and RF designs
• Device modeling and simulation for analog, mixed-signal, and RF designs
• Layout for analog, mixed-signal, and RF designs
• CAD for mixed-domain (semiconductor, nanoelectronic, MEMS, and electro-optical) devices, circuits, and systems

5.1 Biological Systems and Bio-Electronics:
• CAD for biological   computing systems
• CAD for system and synthetic biology
• CAD for bio-electronic devices, sensors, MEMS, and systems
5.2 Nanoscale and Post-CMOS Systems:
• New device structures and process technologies
• New memory technologies (flash, phase change memory, STT-RAM, memristor, etc.)
• Nanotechnologies, nanowires, nanotubes, graphene, etc.
• Quantum computing
• Optical devices and communication
5.3 Design and Optimization for New Electronics and Applications
• Green computing (smart grid, energy, solar panel, etc.)
• Display electronics
• Automobile electronics and eMobility
• Sensors and sensor networks
• Design case studies for multimedia, communication, and consumer electronic applications
• Data Centers


ICCAD serves EDA and design professionals, highlighting new challenges and innovative solutions for Integrated Circuit Design Technologies and Systems. ICCAD covers the full range of CAD topics – from device and circuit-level CAD up through system-level CAD and embedded software, as well as CAD for post-CMOS design and novel application areas, such as biology and nanotechnology.

Paper submissions must be made through the online submission system at the ICCAD web site https://www.easychair.org/account/signin.cgi?conf=iccad2013. Regular papers will be reviewed as finished papers; preliminary submissions will be at a disadvantage.


  • All papers must be in PDF format only, with saveable text.
  • Each paper must be no more than 8 pages (including the abstract, figures, tables, and references), double-columned, 9pt or 10pt font.
  • Your submission must not include information that serves to identify the authors of the manuscript, such as name(s) or affiliation(s) of the author(s), anywhere in the manuscript, abstract, or in the embedded PDF data. References and bibliographic citations to the author(s) own published works or affiliations should be made in the third person.
  • Submissions not adhering to these rules, or determined to be previously published (this includes pre-prints publicly available on personal or other websites, such as arXiv, or publicly available internal memoranda with author names divulged) or simultaneously submitted to another conference, or journal, will be summarily rejected. Internal memoranda with full content not publicly available, and with author names not divulged, may be submitted.

IMPORTANT: Submitted papers must be identical to the final camera-ready version with the following exceptions: inclusion of author names/affiliation, correction of identified errors, addressing reviewer-demanded changes. No other modifications of any kind are allowed including reformatting, restyling, rephrasing, removing figures/results/text, etc. The TPC Chairs reserve the right to finally reject any manuscripts not adhering to these rules. A report detailing all the revisions made must be submitted together with the final camera-ready manuscript once any revision is conducted.

Templates are available on the IEEE website here
*Note to LaTeX Users: Use Type 1 fonts ONLY – do NOT use Type 3 fonts.

The deadline for final papers is Friday, August 9, 2013. Accepted papers are allowed 5 pages in the conference proceedings free of charge. Each additional page beyond 5 pages is charged $125.00 per page. IEEE will hold the copyright for ICCAD 2013 proceedings. Authors of accepted papers must sign an IEEE copyright release form for their paper.

At least one author per accepted paper must register by Friday, September 13 at the discounted speaker’s registration rate. Failure to register will result in your paper being removed from the conference proceedings. IEEE reserves the right to exclude a paper from distribution after the conference (e.g., removal from IEEE Xplore) if the paper is not presented at the conference.

Two papers, one from front-end and one from back-end, will be rewarded with this prestigious award. Two papers, one from front-end and one from back-end, will be rewarded with this prestigious award. The winners will be chosen from nominated papers after a thorough and competitive process by area-specific selection committees and announced at the opening session.

One paper from 2003 and 2004 editions of ICCAD will be selected for this outstanding recognition as evidenced by impact on the research community reflected in citations, on the vendor community via its use in an industrial setting, or by initiating new research venues during the past decade. Nominations from the community are welcome and can be sent to Diana Marculescu, Technical Program Vice-Chair at dianam@cmu.edu.

Authors will be notified of acceptance on or before June 21, 2013. Final paper guidelines will be sent at that time.

Call for Workshop, Embedded Tutorials, Special Sessions, Panels and Keynote Proposals:
DEADLINE: April 30, 2013

Please visit the Call for Proposals page for more information on these areas of ICCAD.

If you need assistance, please contact the appropriate Committee members:
Jörg Henkel, General Chair

Yao-Wen Chang, Technical Program Chair
Diana Marculescu, Technical Program Vice-Chair
Frank Liu, Tutorial and Special Sessions Chair